/*
** Linker Script for 30f2023
*/

OUTPUT_ARCH("30F2023")
CRT0_STARTUP(crt0_standard.o)
CRT1_STARTUP(crt1_standard.o)

OPTIONAL(-lp30F2023)

/*
** Memory Regions
*/
MEMORY
{
  data  (a!xr) : ORIGIN = 0x800,    LENGTH = 512
  program (xr) : ORIGIN = 0x100,    LENGTH = ((4K * 2) - 0x100)
  reset        : ORIGIN = 0,        LENGTH = (4)
  ivt          : ORIGIN = 0x04,     LENGTH = (62 * 2)
  aivt         : ORIGIN = 0x84,     LENGTH = (62 * 2)
  __FBS        : ORIGIN = 0xF80000, LENGTH = (2)
  __FGS        : ORIGIN = 0xF80004, LENGTH = (2)
  __FOSCSEL    : ORIGIN = 0xF80006, LENGTH = (2)
  __FOSC       : ORIGIN = 0xF80008, LENGTH = (2)
  __FWDT       : ORIGIN = 0xF8000A, LENGTH = (2)
  __FPOR       : ORIGIN = 0xF8000C, LENGTH = (2)
  __FICD       : ORIGIN = 0xF8000E, LENGTH = (2)
  __FUID0      : ORIGIN = 0xF80010, LENGTH = (2)
  __FUID1      : ORIGIN = 0xF80012, LENGTH = (2)
}
__NO_HANDLES = 1;          /* Suppress handles on this device  */


/*
** Config Word Addresses
*/
__FBS         = 0xF80000;
__FGS         = 0xF80004;
__FOSCSEL     = 0xF80006;
__FOSC        = 0xF80008;
__FWDT        = 0xF8000A;
__FPOR        = 0xF8000C;
__FICD        = 0xF8000E;
__FUID0       = 0xF80010;
__FUID1       = 0xF80012;


/*
** Base Memory Addresses - Program Memory
*/
__RESET_BASE  = 0;        /* Reset Instruction                */
__IVT_BASE    = 0x04;     /* Interrupt Vector Table           */
__AIVT_BASE   = 0x84;     /* Alternate Interrupt Vector Table */
__CODE_BASE   = 0x100;    /* Handles, User Code, Library Code */


/*
** Base Memory Addresses - Data Memory
*/
__SFR_BASE    = 0;        /* Memory-mapped SFRs                 */
__DATA_BASE   = 0x800;    /* X and General Purpose Data Memory  */
__YDATA_BASE  = 0x0900;   /* Y Data Memory for DSP Instructions */


/*
** ==================== Section Map ======================
*/

SECTIONS
{

  /*
  ** ================== Program Memory =====================
  */

  /*
  ** Reset Instruction
  */
  .reset __RESET_BASE :
  {
        SHORT(ABSOLUTE(__reset));
        SHORT(0x04);
        SHORT((ABSOLUTE(__reset) >> 16) & 0x7F);
        SHORT(0);
  } >reset


  /*
  ** Interrupt Vector Tables
  **
  ** The primary and alternate tables are loaded
  ** here, between sections .reset and .text.
  ** Vector table source code appears below.
  */

  /*
  ** User Code and Library Code
  **
  ** This section must not be assigned to __CODE_BASE,
  ** because CodeGuard(tm) sections may be located there.
  **
  ** Note that input sections *(.text) are not mapped here.
  ** The best-fit allocator locates them, so that .text
  ** may flow around PSV sections as needed.
  */
  .text :
  {
        *(.init);
        *(.user_init);
        *(.handle);
        *(.libc) *(.libm) *(.libdsp);  /* keep together in this order */
        *(.lib*);
  } >program

  /*
  ** User-Defined Section in Program Memory
  **
  ** note: can specify an address using
  **       the following syntax:
  **
  **       usercode 0x1234 :
  **         {
  **           *(usercode);
  **         } >program
  */
  usercode :
  {
        *(usercode);
  } >program


  /*
  ** User-Defined Constants in Program Memory
  **
  ** For PSV type sections, the Load Memory Address (LMA)
  ** should be specified as follows:
  **
  **       userconst : AT(0x1234)
  **         {
  **           *(userconst);
  **         } >program
  **
  ** Note that mapping PSV sections in linker scripts
  ** is not generally recommended.
  **
  ** Because of page alignment restrictions, memory is
  ** often used more efficiently when PSV sections
  ** do not appear in the linker script.
  **
  ** For more information on memory allocation,
  ** please refer to chapter 10, 'Linker Processing'
  ** in the Assembler, Linker manual (DS51317).
  */


  /*
  ** ================ Configuration Memory ================
  */


  /*
  ** Configuration Fuses
  */
  __FBS :
  { *(__FBS.sec) } >__FBS
  __FGS :
  { *(__FGS.sec) } >__FGS
  __FOSCSEL :
  { *(__FOSCSEL.sec) } >__FOSCSEL
  __FOSC :
  { *(__FOSC.sec) } >__FOSC
  __FWDT :
  { *(__FWDT.sec) } >__FWDT
  __FPOR :
  { *(__FPOR.sec) } >__FPOR
  __FICD :
  { *(__FICD.sec) } >__FICD
  __FUID0 :
  { *(__FUID0.sec) } >__FUID0
  __FUID1 :
  { *(__FUID1.sec) } >__FUID1


  /*
  ** ==================== Data Memory ===================
  */

  /* 
  ** ICD Debug Exec
  **
  ** This section provides optional storage for
  ** the ICD2 debugger. Define a global symbol
  ** named __ICD2RAM to enable ICD2. This section
  ** must be loaded at data address 0x800.
  */ 
  .icd __DATA_BASE (NOLOAD): 
  { 
    . += (DEFINED (__ICD2RAM) ? 0x50 : 0 ); 
  } > data 


  /*
  ** User-Defined Section in Data Memory
  **
  ** note: can specify an address using
  **       the following syntax:
  **
  **       userdata 0x1234 :
  **         {
  **           *(userdata);
  **         } >data
  */
  userdata :
  {
        *(userdata);
  } >data


  /*
  ** ===================== Debug Info ====================
  */

  .comment        0 : { *(.comment) }

  /*
  ** DWARF-2
  */
  .debug_info     0 : { *(.debug_info) *(.gnu.linkonce.wi.*) }
  .debug_abbrev   0 : { *(.debug_abbrev) }
  .debug_line     0 : { *(.debug_line) }
  .debug_frame    0 : { *(.debug_frame) }
  .debug_str      0 : { *(.debug_str) }
  .debug_loc      0 : { *(.debug_loc) }
  .debug_macinfo  0 : { *(.debug_macinfo) }
  .debug_pubnames 0 : { *(.debug_pubnames) }
  .debug_ranges   0 : { *(.debug_ranges) }
  .debug_aranges  0 : { *(.debug_aranges) }

} /* SECTIONS */

/*
** ================= End of Section Map ================
*/
/*
** Section Map for Interrupt Vector Tables
*/
SECTIONS
{

/*
** Primary Interrupt Vector Table
*/
.ivt __IVT_BASE :
  {
    LONG(DEFINED(__ReservedTrap0)  ? ABSOLUTE(__ReservedTrap0)  :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__OscillatorFail) ? ABSOLUTE(__OscillatorFail) :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__AddressError)   ? ABSOLUTE(__AddressError)   :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__StackError)     ? ABSOLUTE(__StackError)     :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__MathError)      ? ABSOLUTE(__MathError)      :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__ReservedTrap5)  ? ABSOLUTE(__ReservedTrap5)  :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__ReservedTrap6)  ? ABSOLUTE(__ReservedTrap6)  :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__ReservedTrap7)  ? ABSOLUTE(__ReservedTrap7)  :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__INT0Interrupt)  ? ABSOLUTE(__INT0Interrupt)  :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__IC1Interrupt)   ? ABSOLUTE(__IC1Interrupt)   :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__OC1Interrupt)   ? ABSOLUTE(__OC1Interrupt)   :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__T1Interrupt)    ? ABSOLUTE(__T1Interrupt)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt4)     ? ABSOLUTE(__Interrupt4)     :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__OC2Interrupt)   ? ABSOLUTE(__OC2Interrupt)   :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__T2Interrupt)    ? ABSOLUTE(__T2Interrupt)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__T3Interrupt)    ? ABSOLUTE(__T3Interrupt)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__SPI1Interrupt)  ? ABSOLUTE(__SPI1Interrupt)  :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__U1RXInterrupt)  ? ABSOLUTE(__U1RXInterrupt)  :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__U1TXInterrupt)  ? ABSOLUTE(__U1TXInterrupt)  :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__ADCInterrupt)   ? ABSOLUTE(__ADCInterrupt)   :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__NVMInterrupt)   ? ABSOLUTE(__NVMInterrupt)   :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__SI2CInterrupt)  ? ABSOLUTE(__SI2CInterrupt)  :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__MI2CInterrupt)  ? ABSOLUTE(__MI2CInterrupt)  :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt15)    ? ABSOLUTE(__Interrupt15)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__INT1Interrupt)  ? ABSOLUTE(__INT1Interrupt)  :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__INT2Interrupt)  ? ABSOLUTE(__INT2Interrupt)  :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__PWMSpEventMatchInterrupt)   ? ABSOLUTE(__PWMSpEventMatchInterrupt)   :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__PWM1Interrupt)  ? ABSOLUTE(__PWM1Interrupt)  :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__PWM2Interrupt)  ? ABSOLUTE(__PWM2Interrupt)  :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__PWM3Interrupt)  ? ABSOLUTE(__PWM3Interrupt)  :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__PWM4Interrupt)  ? ABSOLUTE(__PWM4Interrupt)  :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt23)    ? ABSOLUTE(__Interrupt23)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt24)    ? ABSOLUTE(__Interrupt24)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt25)    ? ABSOLUTE(__Interrupt25)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt26)    ? ABSOLUTE(__Interrupt26)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__CNInterrupt)    ? ABSOLUTE(__CNInterrupt)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt28)    ? ABSOLUTE(__Interrupt28)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__CMP1Interrupt)  ? ABSOLUTE(__CMP1Interrupt)  :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__CMP2Interrupt)  ? ABSOLUTE(__CMP2Interrupt)  :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__CMP3Interrupt)  ? ABSOLUTE(__CMP3Interrupt)  :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__CMP4Interrupt)  ? ABSOLUTE(__CMP4Interrupt)  :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt33)    ? ABSOLUTE(__Interrupt33)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt34)    ? ABSOLUTE(__Interrupt34)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt35)    ? ABSOLUTE(__Interrupt35)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt36)    ? ABSOLUTE(__Interrupt36)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__ADCP0Interrupt) ? ABSOLUTE(__ADCP0Interrupt) :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__ADCP1Interrupt) ? ABSOLUTE(__ADCP1Interrupt) :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__ADCP2Interrupt) ? ABSOLUTE(__ADCP2Interrupt) :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__ADCP3Interrupt) ? ABSOLUTE(__ADCP3Interrupt) :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__ADCP4Interrupt) ? ABSOLUTE(__ADCP4Interrupt) :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__ADCP5Interrupt) ? ABSOLUTE(__ADCP5Interrupt) :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt43)    ? ABSOLUTE(__Interrupt43)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt44)    ? ABSOLUTE(__Interrupt44)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt45)    ? ABSOLUTE(__Interrupt45)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt46)    ? ABSOLUTE(__Interrupt46)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt47)    ? ABSOLUTE(__Interrupt47)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt48)    ? ABSOLUTE(__Interrupt48)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt49)    ? ABSOLUTE(__Interrupt49)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt50)    ? ABSOLUTE(__Interrupt50)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt51)    ? ABSOLUTE(__Interrupt51)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt52)    ? ABSOLUTE(__Interrupt52)    :
         ABSOLUTE(__DefaultInterrupt));
    LONG(DEFINED(__Interrupt53)    ? ABSOLUTE(__Interrupt53)    :
         ABSOLUTE(__DefaultInterrupt));
  } >ivt


/*
** Alternate Interrupt Vector Table
*/
.aivt __AIVT_BASE :
  {
    LONG(DEFINED(__AltReservedTrap0)  ? ABSOLUTE(__AltReservedTrap0)  :
        (DEFINED(__ReservedTrap0)     ? ABSOLUTE(__ReservedTrap0)     :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltOscillatorFail) ? ABSOLUTE(__AltOscillatorFail) :
        (DEFINED(__OscillatorFail)    ? ABSOLUTE(__OscillatorFail)    :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltAddressError)   ? ABSOLUTE(__AltAddressError)   :
        (DEFINED(__AddressError)      ? ABSOLUTE(__AddressError)      :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltStackError)     ? ABSOLUTE(__AltStackError)     :
        (DEFINED(__StackError)        ? ABSOLUTE(__StackError)        :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltMathError)      ? ABSOLUTE(__AltMathError)      :
        (DEFINED(__MathError)         ? ABSOLUTE(__MathError)         :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltReservedTrap5)  ? ABSOLUTE(__AltReservedTrap5)  :
        (DEFINED(__ReservedTrap5)     ? ABSOLUTE(__ReservedTrap5)     :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltReservedTrap6)  ? ABSOLUTE(__AltReservedTrap6)  :
        (DEFINED(__ReservedTrap6)     ? ABSOLUTE(__ReservedTrap6)     :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltReservedTrap7)  ? ABSOLUTE(__AltReservedTrap7)  :
        (DEFINED(__ReservedTrap7)     ? ABSOLUTE(__ReservedTrap7)     :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltINT0Interrupt)  ? ABSOLUTE(__AltINT0Interrupt)  :
        (DEFINED(__INT0Interrupt)     ? ABSOLUTE(__INT0Interrupt)     :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltIC1Interrupt)   ? ABSOLUTE(__AltIC1Interrupt)   :
        (DEFINED(__IC1Interrupt)      ? ABSOLUTE(__IC1Interrupt)      :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltOC1Interrupt)   ? ABSOLUTE(__AltOC1Interrupt)   :
        (DEFINED(__OC1Interrupt)      ? ABSOLUTE(__OC1Interrupt)      :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltT1Interrupt)    ? ABSOLUTE(__AltT1Interrupt)    :
        (DEFINED(__T1Interrupt)       ? ABSOLUTE(__T1Interrupt)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt4)     ? ABSOLUTE(__AltInterrupt4)     :
        (DEFINED(__Interrupt4)        ? ABSOLUTE(__Interrupt4)        :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltOC2Interrupt)   ? ABSOLUTE(__AltOC2Interrupt)   :
        (DEFINED(__OC2Interrupt)      ? ABSOLUTE(__OC2Interrupt)      :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltT2Interrupt)    ? ABSOLUTE(__AltT2Interrupt)    :
        (DEFINED(__T2Interrupt)       ? ABSOLUTE(__T2Interrupt)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltT3Interrupt)    ? ABSOLUTE(__AltT3Interrupt)    :
        (DEFINED(__T3Interrupt)       ? ABSOLUTE(__T3Interrupt)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltSPI1Interrupt)  ? ABSOLUTE(__AltSPI1Interrupt)  :
        (DEFINED(__SPI1Interrupt)     ? ABSOLUTE(__SPI1Interrupt)     :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltU1RXInterrupt)  ? ABSOLUTE(__AltU1RXInterrupt)  :
        (DEFINED(__U1RXInterrupt)     ? ABSOLUTE(__U1RXInterrupt)     :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltU1TXInterrupt)  ? ABSOLUTE(__AltU1TXInterrupt)  :
        (DEFINED(__U1TXInterrupt)     ? ABSOLUTE(__U1TXInterrupt)     :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltADCInterrupt)   ? ABSOLUTE(__AltADCInterrupt)   :
        (DEFINED(__ADCInterrupt)      ? ABSOLUTE(__ADCInterrupt)      :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltNVMInterrupt)   ? ABSOLUTE(__AltNVMInterrupt)   :
        (DEFINED(__NVMInterrupt)      ? ABSOLUTE(__NVMInterrupt)      :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltSI2CInterrupt)  ? ABSOLUTE(__AltSI2CInterrupt)  :
        (DEFINED(__SI2CInterrupt)     ? ABSOLUTE(__SI2CInterrupt)     :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltMI2CInterrupt)  ? ABSOLUTE(__AltMI2CInterrupt)  :
        (DEFINED(__MI2CInterrupt)     ? ABSOLUTE(__MI2CInterrupt)     :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt15)    ? ABSOLUTE(__AltInterrupt15)    :
        (DEFINED(__Interrupt15)       ? ABSOLUTE(__Interrupt15)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltINT1Interrupt)  ? ABSOLUTE(__AltINT1Interrupt)  :
        (DEFINED(__INT1Interrupt)     ? ABSOLUTE(__INT1Interrupt)     :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltINT2Interrupt)  ? ABSOLUTE(__AltINT2Interrupt)  :
        (DEFINED(__INT2Interrupt)     ? ABSOLUTE(__INT2Interrupt)     :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltPWMSpEventMatchInterrupt)   ? ABSOLUTE(__AltPWMSpEventMatchInterrupt)   :
        (DEFINED(__PWMSpEventMatchInterrupt)      ? ABSOLUTE(__PWMSpEventMatchInterrupt)      :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltPWM1Interrupt)  ? ABSOLUTE(__AltPWM1Interrupt)  :
        (DEFINED(__PWM1Interrupt)     ? ABSOLUTE(__PWM1Interrupt)     :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltPWM2Interrupt)  ? ABSOLUTE(__AltPWM2Interrupt)  :
        (DEFINED(__PWM2Interrupt)     ? ABSOLUTE(__PWM2Interrupt)     :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltPWM3Interrupt)  ? ABSOLUTE(__AltPWM3Interrupt)  :
        (DEFINED(__PWM3Interrupt)     ? ABSOLUTE(__PWM3Interrupt)     :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltPWM4Interrupt)  ? ABSOLUTE(__AltPWM4Interrupt)  :
        (DEFINED(__PWM4Interrupt)     ? ABSOLUTE(__PWM4Interrupt)     :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt23)    ? ABSOLUTE(__AltInterrupt23)    :
        (DEFINED(__Interrupt23)       ? ABSOLUTE(__Interrupt23)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt24)    ? ABSOLUTE(__AltInterrupt24)    :
        (DEFINED(__Interrupt24)       ? ABSOLUTE(__Interrupt24)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt25)    ? ABSOLUTE(__AltInterrupt25)    :
        (DEFINED(__Interrupt25)       ? ABSOLUTE(__Interrupt25)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt26)    ? ABSOLUTE(__AltInterrupt26)    :
        (DEFINED(__Interrupt26)       ? ABSOLUTE(__Interrupt26)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltCNInterrupt)    ? ABSOLUTE(__AltCNInterrupt)    :
        (DEFINED(__CNInterrupt)       ? ABSOLUTE(__CNInterrupt)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt28)    ? ABSOLUTE(__AltInterrupt28)    :
        (DEFINED(__Interrupt28)       ? ABSOLUTE(__Interrupt28)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltCMP1Interrupt)  ? ABSOLUTE(__AltCMP1Interrupt)  :
        (DEFINED(__CMP1Interrupt)     ? ABSOLUTE(__CMP1Interrupt)     :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltCMP2Interrupt)  ? ABSOLUTE(__AltCMP2Interrupt)  :
        (DEFINED(__CMP2Interrupt)     ? ABSOLUTE(__CMP2Interrupt)     :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltCMP3Interrupt)  ? ABSOLUTE(__AltCMP3Interrupt)  :
        (DEFINED(__CMP3Interrupt)     ? ABSOLUTE(__CMP3Interrupt)     :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltCMP4Interrupt)  ? ABSOLUTE(__AltCMP4Interrupt)  :
        (DEFINED(__CMP4Interrupt)     ? ABSOLUTE(__CMP4Interrupt)     :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt33)    ? ABSOLUTE(__AltInterrupt33)    :
        (DEFINED(__Interrupt33)       ? ABSOLUTE(__Interrupt33)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt34)    ? ABSOLUTE(__AltInterrupt34)    :
        (DEFINED(__Interrupt34)       ? ABSOLUTE(__Interrupt34)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt35)    ? ABSOLUTE(__AltInterrupt35)    :
        (DEFINED(__Interrupt35)       ? ABSOLUTE(__Interrupt35)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt36)    ? ABSOLUTE(__AltInterrupt36)    :
        (DEFINED(__Interrupt36)       ? ABSOLUTE(__Interrupt36)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltADCP0Interrupt) ? ABSOLUTE(__AltADCP0Interrupt) :
        (DEFINED(__ADCP0Interrupt)    ? ABSOLUTE(__ADCP0Interrupt)    :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltADCP1Interrupt) ? ABSOLUTE(__AltADCP1Interrupt) :
        (DEFINED(__ADCP1Interrupt)    ? ABSOLUTE(__ADCP1Interrupt)    :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltADCP2Interrupt) ? ABSOLUTE(__AltADCP2Interrupt) :
        (DEFINED(__ADCP2Interrupt)    ? ABSOLUTE(__ADCP2Interrupt)    :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltADCP3Interrupt) ? ABSOLUTE(__AltADCP3Interrupt) :
        (DEFINED(__ADCP3Interrupt)    ? ABSOLUTE(__ADCP3Interrupt)    :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltADCP4Interrupt) ? ABSOLUTE(__AltADCP4Interrupt) :
        (DEFINED(__ADCP4Interrupt)    ? ABSOLUTE(__ADCP4Interrupt)    :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltADCP5Interrupt) ? ABSOLUTE(__AltADCP5Interrupt) :
        (DEFINED(__ADCP5Interrupt)    ? ABSOLUTE(__ADCP5Interrupt)    :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt43)    ? ABSOLUTE(__AltInterrupt43)    :
        (DEFINED(__Interrupt43)       ? ABSOLUTE(__Interrupt43)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt44)    ? ABSOLUTE(__AltInterrupt44)    :
        (DEFINED(__Interrupt44)       ? ABSOLUTE(__Interrupt44)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt45)    ? ABSOLUTE(__AltInterrupt45)    :
        (DEFINED(__Interrupt45)       ? ABSOLUTE(__Interrupt45)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt46)    ? ABSOLUTE(__AltInterrupt46)    :
        (DEFINED(__Interrupt46)       ? ABSOLUTE(__Interrupt46)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt47)    ? ABSOLUTE(__AltInterrupt47)    :
        (DEFINED(__Interrupt47)       ? ABSOLUTE(__Interrupt47)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt48)    ? ABSOLUTE(__AltInterrupt48)    :
        (DEFINED(__Interrupt48)       ? ABSOLUTE(__Interrupt48)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt49)    ? ABSOLUTE(__AltInterrupt49)    :
        (DEFINED(__Interrupt49)       ? ABSOLUTE(__Interrupt49)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt50)    ? ABSOLUTE(__AltInterrupt50)    :
        (DEFINED(__Interrupt50)       ? ABSOLUTE(__Interrupt50)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt51)    ? ABSOLUTE(__AltInterrupt51)    :
        (DEFINED(__Interrupt51)       ? ABSOLUTE(__Interrupt51)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt52)    ? ABSOLUTE(__AltInterrupt52)    :
        (DEFINED(__Interrupt52)       ? ABSOLUTE(__Interrupt52)       :
         ABSOLUTE(__DefaultInterrupt)));
    LONG(DEFINED(__AltInterrupt53)    ? ABSOLUTE(__AltInterrupt53)    :
        (DEFINED(__Interrupt53)       ? ABSOLUTE(__Interrupt53)       :
         ABSOLUTE(__DefaultInterrupt)));
  } >aivt

} /* SECTIONS */


/* File Description | Notes:
** =========================
** 1] This file maps special function register(SFR) names used in the datasheet
**   to memory locations in the PIC30Fxxxx device. The memory locations are
**    byte addresses. The PIC30Fxxxx is a family of byte addressable devices.
** 2] The register names used in this file are taken to match the
**    PIC30Fxxxx data sheets as closely as possible.
** 3] SFR address definitions are listed in the ascending order of memory
**    addresses and are grouped based on the module they belong to. For e.g.,
**    WREG10 is listed before ACCAL, and the Core SFRs are grouped
**    separately, prior to the Interrupt Controller SFRs or the General
**    Purpose Timer SFRs.
** 4] SFR names exactly match names in the device specific C "header" file
**    and the Assembly "include" file. Any changes to names in one of these
**    files, calls for similar changes in the other two.
**
* Revision History:
** =================
**-------------------------------------------------------------------------
**Rev:   Date:        Details:                                    Who:
**-------------------------------------------------------------------------
**1.0   06 Jun 2006  Device linker provides from superset   S Fernandes 
**1.1   29 Sep 2006  Deleted CNEN2 and CNPU2, added INTTREG  S Khare
**1.4   09 Oct 2006  Corrected IPC9bits and IPC10bits        S Khare  
**1.5   17 Oct 2006  Corrected SPI register addresses        S Khare 
**1.8   13 Nov 2006  Added CNEN1bits and CNPU1bits addresses S Khare
**-------------------------------------------------------------------------
**
**
***************************************************************************/


/*=========================================================================
**       Register Definitions
** (Core and Peripheral Registers in Data Space)
**==========================================================================
**
**==========================================================================
**
**       dsPIC Core Register Definitions
**
**=========================================================================*/
 WREG0 = 0x0000;
_WREG0 = 0x0000;
 WREG1 = 0x0002;
_WREG1 = 0x0002;
 WREG2 = 0x0004;
_WREG2 = 0x0004;
 WREG3 = 0x0006;
_WREG3 = 0x0006;
 WREG4 = 0x0008;
_WREG4 = 0x0008;
 WREG5 = 0x000A;
_WREG5 = 0x000A;
 WREG6 = 0x000C;
_WREG6 = 0x000C;
 WREG7 = 0x000E;
_WREG7 = 0x000E;
 WREG8 = 0x0010;
_WREG8 = 0x0010;
 WREG9 = 0x0012;
_WREG9 = 0x0012;
 WREG10 = 0x0014;
_WREG10 = 0x0014;
 WREG11 = 0x0016;
_WREG11 = 0x0016;
 WREG12 = 0x0018;
_WREG12 = 0x0018;
 WREG13 = 0x001A;
_WREG13 = 0x001A;
 WREG14 = 0x001C;
_WREG14 = 0x001C;
 WREG15 = 0x001E;
_WREG15 = 0x001E;
 SPLIM = 0x0020;
_SPLIM = 0x0020;
 ACCAL = 0x0022;
_ACCAL = 0x0022;
 ACCAH = 0x0024;
_ACCAH = 0x0024;
 ACCAU = 0x0026;
_ACCAU = 0x0026;
 ACCBL = 0x0028;
_ACCBL = 0x0028;
 ACCBH = 0x002A;
_ACCBH = 0x002A;
 ACCBU = 0x002C;
_ACCBU = 0x002C;
 PCL = 0x002E;
_PCL = 0x002E;
 PCH = 0x0030;
_PCH = 0x0030;
 TBLPAG = 0x0032;
_TBLPAG = 0x0032;
 PSVPAG = 0x0034;
_PSVPAG = 0x0034;
 RCOUNT = 0x0036;
_RCOUNT = 0x0036;
 DCOUNT = 0x0038;
_DCOUNT = 0x0038;
 DOSTARTL = 0x003A;
_DOSTARTL = 0x003A;
 DOSTARTH = 0x003C;
_DOSTARTH = 0x003C;
 DOENDL = 0x003E;
_DOENDL = 0x003E;
 DOENDH = 0x0040;
_DOENDH = 0x0040;
 SR = 0x0042;
_SR = 0x0042;
 CORCON = 0x0044;
_CORCON = 0x0044;
 MODCON = 0x0046;
_MODCON = 0x0046;
 XMODSRT = 0x0048;
_XMODSRT = 0x0048;
 XMODEND = 0x004A;
_XMODEND = 0x004A;
 YMODSRT = 0x004C;
_YMODSRT = 0x004C;
 YMODEND = 0x004E;
_YMODEND = 0x004E;
 XBREV = 0x0050;
_XBREV = 0x0050;
 DISICNT = 0x0052;
_DISICNT = 0x0052;

/*==========================================================================
**
**           Change Notification Register Definitions
**
==========================================================================*/

 CNEN1 = 0x0060;
_CNEN1 = 0x0060;
 CNPU1 = 0x0068;
_CNPU1 = 0x0068;

/*==========================================================================
**
**           Interrupt Controller Register Definitions
**
==========================================================================*/
 INTCON1 = 0x0080;
_INTCON1 = 0x0080;
 INTCON2 = 0x0082;
_INTCON2 = 0x0082;
 IFS0 = 0x0084;
_IFS0 = 0x0084;
 IFS1 = 0x0086;
_IFS1 = 0x0086;
 IFS2 = 0x0088;
_IFS2 = 0x0088;
 IEC0 = 0x0094;
_IEC0 = 0x0094;
 IEC1 = 0x0096;
_IEC1 = 0x0096;
 IEC2 = 0x0098;
_IEC2 = 0x0098;
 IPC0 = 0x00A4;
_IPC0 = 0x00A4;
 IPC1 = 0x00A6;
_IPC1 = 0x00A6;
 IPC2 = 0x00A8;
_IPC2 = 0x00A8;
 IPC3 = 0x00AA;
_IPC3 = 0x00AA;
 IPC4 = 0x00AC;
_IPC4 = 0x00AC;
 IPC5 = 0x00AE;
_IPC5 = 0x00AE;
 IPC6 = 0x00B0;
_IPC6 = 0x00B0;
 IPC7 = 0x00B2;
_IPC7 = 0x00B2;
 IPC8 = 0x00B4;
_IPC8 = 0x00B4;
 IPC9 = 0x00B6;
_IPC9 = 0x00B6;
 IPC10 = 0x00B8;
_IPC10 = 0x00B8;
 INTTREG = 0x00E0;
_INTTREG = 0x00E0;

/*=========================================================================
**
**       Timer  Module Register Definitions
**
===========================================================================*/
/*--------------Timer 1 Module---------------------------------------------*/
 TMR1 = 0x0100;
_TMR1 = 0x0100;
 PR1 = 0x0102;
_PR1 = 0x0102;
 T1CON = 0x0104;
_T1CON = 0x0104;

/*--------------Timer2/3 Module--------------------------------------------*/
 TMR2 = 0x0106;
_TMR2 = 0x0106;
 TMR3HLD = 0x0108;
_TMR3HLD = 0x0108;
 TMR3 = 0x010A;
_TMR3 = 0x010A;
 PR2 = 0x010C;
_PR2 = 0x010C;
 PR3 = 0x010E;
_PR3 = 0x010E;
 T2CON = 0x0110;
_T2CON = 0x0110;
 T3CON = 0x0112;
_T3CON = 0x0112;


/*=========================================================================
**
**       Input Capture Module Register Definitions
**
=========================================================================*/
 IC1BUF = 0x0140;
_IC1BUF = 0x0140;
 IC1CON = 0x0142;
_IC1CON = 0x0142;


/*==========================================================================
**
**       Output Compare Module Register Definitions
**
===========================================================================*/
 OC1RS = 0x0180;
_OC1RS = 0x0180;
 OC1R = 0x0182;
_OC1R = 0x0182;
 OC1CON = 0x0184;
_OC1CON = 0x0184;
 OC2RS = 0x0186;
_OC2RS = 0x0186;
 OC2R = 0x0188;
_OC2R = 0x0188;
 OC2CON = 0x018A;
_OC2CON = 0x018A;


/*=========================================================================
**
**       Inter-Integrated Circuit(I2C) Module Register Definitions
**
==========================================================================*/
 I2CRCV = 0x0200;
_I2CRCV = 0x0200;
 I2CTRN = 0x0202;
_I2CTRN = 0x0202;
 I2CBRG = 0x0204;
_I2CBRG = 0x0204;
 I2CCON = 0x0206;
_I2CCON = 0x0206;
 I2CSTAT = 0x0208;
_I2CSTAT = 0x0208;
 I2CADD = 0x020A;
_I2CADD = 0x020A;


/*==========================================================================
**
**          Universal Asynchronous Receiver TransmitterUART Module
**                           Register Definitions
**
==========================================================================*/
/*------------------UART 1 Module-----------------------------------------*/
 U1MODE = 0x0220;
_U1MODE = 0x0220;
 U1STA = 0x0222;
_U1STA = 0x0222;
 U1TXREG = 0x0224;
_U1TXREG = 0x0224;
 U1RXREG = 0x0226;
_U1RXREG = 0x0226;
 U1BRG = 0x0228;
_U1BRG = 0x0228;


/*==========================================================================
**
**       Serial Peripheral Interface(SPI) Module Register Definitions
**
==========================================================================*/
/*-----------------SPI 1 Module-------------------------------------------*/
 SPI1STAT = 0x0240;
_SPI1STAT = 0x0240;
 SPI1CON1 = 0x0242;
_SPI1CON1 = 0x0242;
 SPI1CON2 = 0x0244;
_SPI1CON2 = 0x0244;
 SPI1BUF = 0x0246;
_SPI1BUF = 0x0246;


/*==========================================================================
**
**    General Purpose I/O Port Register Definitions
**
==========================================================================*/
 TRISA = 0x02C0;
_TRISA = 0x02C0;
 PORTA = 0x02C2;
_PORTA = 0x02C2;
 LATA = 0x02C4;
_LATA = 0x02C4;

 TRISB = 0x02C6;
_TRISB = 0x02C6;
 PORTB = 0x02C8;
_PORTB = 0x02C8;
 LATB = 0x02CA;
_LATB = 0x02CA;

 TRISD = 0x02D2;
_TRISD = 0x02D2;
 PORTD = 0x02D4;
_PORTD = 0x02D4;
 LATD = 0x02D6;
_LATD = 0x02D6;

 TRISE = 0x02D8;
_TRISE = 0x02D8;
 PORTE = 0x02DA;
_PORTE = 0x02DA;
 LATE = 0x02DC;
_LATE = 0x02DC;

 TRISF = 0x02DE;
_TRISF = 0x02DE;
 PORTF = 0x02E0;
_PORTF = 0x02E0;
 LATF = 0x02E2;
_LATF = 0x02E2;

 TRISG = 0x02E4;
_TRISG = 0x02E4;
 PORTG = 0x02E6;
_PORTG = 0x02E6;
 LATG = 0x02E8;
_LATG = 0x02E8;


/*==========================================================================
**
**    A/D converter registers
**
==========================================================================*/
 ADCON = 0x0300;
_ADCON = 0x0300;
 ADPCFG = 0x0302;
_ADPCFG = 0x0302;
 ADSTAT = 0x0306;
_ADSTAT = 0x0306;
 ADBASE = 0x0308;
_ADBASE = 0x0308;
 ADCPC0 = 0x030A;
_ADCPC0 = 0x030A;
 ADCPC1 = 0x030C;
_ADCPC1 = 0x030C;
 ADCPC2 = 0x030E;
_ADCPC2 = 0x030E;
 ADCBUF0 = 0x0320;
_ADCBUF0 = 0x0320;
 ADCBUF1 = 0x0322;
_ADCBUF1 = 0x0322;
 ADCBUF2 = 0x0324;
_ADCBUF2 = 0x0324;
 ADCBUF3 = 0x0326;
_ADCBUF3 = 0x0326;
 ADCBUF4 = 0x0328;
_ADCBUF4 = 0x0328;
 ADCBUF5 = 0x032A;
_ADCBUF5 = 0x032A;
 ADCBUF6 = 0x032C;
_ADCBUF6 = 0x032C;
 ADCBUF7 = 0x032E;
_ADCBUF7 = 0x032E;
 ADCBUF8 = 0x0330;
_ADCBUF8 = 0x0330;
 ADCBUF9 = 0x0332;
_ADCBUF9 = 0x0332;
 ADCBUFA = 0x0334;
_ADCBUFA = 0x0334;
 ADCBUFB = 0x0336;
_ADCBUFB = 0x0336;
 ADCBUF10 = 0x0334;
_ADCBUF10 = 0x0334;
 ADCBUF11 = 0x0336;
_ADCBUF11 = 0x0336;

/*==========================================================================
**
**    PWM Registers
**
==========================================================================*/
 PTCON = 0x0400;
_PTCON = 0x0400;
 PTPER = 0x0402;
_PTPER = 0x0402;
 MDC = 0x0404;
_MDC = 0x0404;
 SEVTCMP = 0x0406;
_SEVTCMP = 0x0406;

 PWMCON1 = 	0x0408;
_PWMCON1 = 	0x0408;
 IOCON1 = 	0x040A;
_IOCON1 = 	0x040A;
 FCLCON1 = 	0x040C;
_FCLCON1 = 	0x040C;
 PDC1 = 	0x040E;
_PDC1 = 	0x040E;
 PHASE1 = 	0x0410;
_PHASE1 = 	0x0410;
 DTR1 = 	0x0412;
_DTR1 = 	0x0412;
 ALTDTR1 = 	0x0414;
_ALTDTR1 = 	0x0414;
 TRIG1 = 	0x0416;
_TRIG1 = 	0x0416;
 TRGCON1 = 	0x0418;
_TRGCON1 = 	0x0418;
 LEBCON1 = 	0x041A;
_LEBCON1 = 	0x041A;

 PWMCON2 = 	0x041C;
_PWMCON2 = 	0x041C;
 IOCON2 = 	0x041E;
_IOCON2 = 	0x041E;
 FCLCON2 = 	0x0420;
_FCLCON2 = 	0x0420;
 PDC2 = 	0x0422;
_PDC2 = 	0x0422;
 PHASE2 = 	0x0424;
_PHASE2 = 	0x0424;
 DTR2 = 	0x0426;
_DTR2 = 	0x0426;
 ALTDTR2 = 	0x0428;
_ALTDTR2 = 	0x0428;
 TRIG2 = 	0x042A;
_TRIG2 = 	0x042A;
 TRGCON2 = 	0x042C;
_TRGCON2 = 	0x042C;
 LEBCON2 = 	0x042E;
_LEBCON2 = 	0x042E;



 PWMCON3 = 	0x0430;
_PWMCON3 = 	0x0430;
 IOCON3 = 	0x0432;
_IOCON3 = 	0x0432;
 FCLCON3 = 	0x0434;
_FCLCON3 = 	0x0434;
 PDC3 = 	0x0436;
_PDC3 = 	0x0436;
 PHASE3 = 	0x0438;
_PHASE3 = 	0x0438;
 DTR3 = 	0x043A;
_DTR3 = 	0x043A;
 ALTDTR3 = 	0x043C;
_ALTDTR3 = 	0x043C;
 TRIG3 = 	0x043E;
_TRIG3 = 	0x043E;
 TRGCON3 = 	0x0440;
_TRGCON3 = 	0x0440;
 LEBCON3 = 	0x0442;
_LEBCON3 = 	0x0442;

 PWMCON4 = 	0x0444;
_PWMCON4 = 	0x0444;
 IOCON4 = 	0x0446;
_IOCON4 = 	0x0446;
 FCLCON4 = 	0x0448;
_FCLCON4 = 	0x0448;
 PDC4 = 	0x044A;
_PDC4 = 	0x044A;
 PHASE4 = 	0x044C;
_PHASE4 = 	0x044C;
 DTR4 = 	0x044E;
_DTR4 = 	0x044E;
 ALTDTR4 = 	0x0450;
_ALTDTR4 = 	0x0450;
 TRIG4 = 	0x0452;
_TRIG4 = 	0x0452;
 TRGCON4 = 	0x0454;
_TRGCON4 = 	0x0454;
 LEBCON4 =  0x0456;
_LEBCON4 = 	0x0456;

/*==========================================================================
**
** Analog Comparator Definitions
**
==========================================================================*/
 CMPCON1 = 0x04C0;
_CMPCON1 = 0x04C0;
 CMPDAC1 = 0x04C2;
_CMPDAC1 = 0x04C2;
 CMPCON2 = 0x04C4;
_CMPCON2 = 0x04C4;
 CMPDAC2 = 0x04C6;
_CMPDAC2 = 0x04C6;
 CMPCON3 = 0x04C8;
_CMPCON3 = 0x04C8;
 CMPDAC3 = 0x04CA;
_CMPDAC3 = 0x04CA;
 CMPCON4 = 0x04CC;
_CMPCON4 = 0x04CC;
 CMPDAC4 = 0x04CE;
_CMPDAC4 = 0x04CE;


/*==========================================================================
**
**    System Integration Block Registers
**
==========================================================================*/
 RCON = 0x0740;
_RCON = 0x0740;
 OSCCON = 0x0742;
_OSCCON = 0x0742;
 CLKDIV = 0x0744;
_CLKDIV = 0x0744;
 OSCTUN = 0x0748;
_OSCTUN = 0x0748;
 OSCTUN2 = 0x074A;
_OSCTUN2 = 0x074A;
 LFSR = 0x074C;
_LFSR = 0x074C;
OSCCONL = OSCCON;
_OSCCONL = OSCCON;
OSCCONH = OSCCON + 1;
_OSCCONH = OSCCON + 1;

/*==========================================================================
**
**    Non Volatile Memory Registers
**
==========================================================================*/
 NVMCON = 0x0760;
_NVMCON = 0x0760;
 NVMADR = 0x0762;
_NVMADR = 0x0762;
 NVMADRU = 0x0764;
_NVMADRU = 0x0764;
 NVMKEY = 0x0766;
_NVMKEY = 0x0766;

/*==========================================================================
**
**   Peripheral Module Disable Registers
**
==========================================================================*/
 PMD1 = 0x0770;
_PMD1 = 0x0770;
 PMD2 = 0x0772;
_PMD2 = 0x0772;
 PMD3 = 0x0774;
_PMD3 = 0x0774;

/*
**End of SFR Definitions required for both C and Assembly files
*/


/*=========================================================================
**
**Start of Additional SFR Definitions that are required specifically
**for the C header file.
**
==========================================================================*/
 ACCA = 0x0022;
_ACCA = 0x0022;
 ACCB = 0x0028;
_ACCB = 0x0028;
 SRbits = 0x0042;
_SRbits = 0x0042;
 CORCONbits = 0x0044;
_CORCONbits = 0x0044;
 MODCONbits = 0x0046;
_MODCONbits = 0x0046;
 XBREVbits = 0x0050;
_XBREVbits = 0x0050;
_CNEN1bits = 0x0060;
 CNEN1bits = 0x0060;
_CNPU1bits = 0x0064;
 CNPU1bits = 0x0064;
 INTCON1bits = 0x0080;
_INTCON1bits = 0x0080;
 INTCON2bits = 0x0082;
_INTCON2bits = 0x0082;
 IFS0bits = 0x0084;
_IFS0bits = 0x0084;
 IFS1bits = 0x0086;
_IFS1bits = 0x0086;
 IFS2bits = 0x0088;
_IFS2bits = 0x0088;
 IEC0bits = 0x0094;
_IEC0bits = 0x0094;
 IEC1bits = 0x0096;
_IEC1bits = 0x0096;
 IEC2bits = 0x0098;
_IEC2bits = 0x0098;
 IPC0bits = 0x00A4;
_IPC0bits = 0x00A4;
 IPC1bits = 0x00A6;
_IPC1bits = 0x00A6;
 IPC2bits = 0x00A8;
_IPC2bits = 0x00A8;
 IPC3bits = 0x00AA;
_IPC3bits = 0x00AA;
 IPC4bits = 0x00AC;
_IPC4bits = 0x00AC;
 IPC5bits = 0x00AE;
_IPC5bits = 0x00AE;
 IPC6bits = 0x00B0;
_IPC6bits = 0x00B0;
 IPC7bits = 0x00B2;
_IPC7bits = 0x00B2;
 IPC8bits = 0x00B4;
_IPC8bits = 0x00B4;
 IPC9bits = 0x00B6;
_IPC9bits = 0x00B6;
 IPC10bits = 0x00B8;
_IPC10bits = 0x00B8;
 T1CONbits = 0x0104;
_T1CONbits = 0x0104;
 T2CONbits = 0x0110;
_T2CONbits = 0x0110;
 T3CONbits = 0x0112;
_T3CONbits = 0x0112;
 IC1CONbits = 0x0142;
_IC1CONbits = 0x0142;
 OC1CONbits = 0x0184;
_OC1CONbits = 0x0184;
 OC2CONbits = 0x018A;
_OC2CONbits = 0x018A;
 I2CCONbits = 0x0206;
_I2CCONbits = 0x0206;
 I2CSTATbits = 0x0208;
_I2CSTATbits = 0x0208;
 U1MODEbits = 0x0220;
_U1MODEbits = 0x0220;
 U1STAbits = 0x0222;
_U1STAbits = 0x0222;
 SPI1STATbits = 0x0240;
_SPI1STATbits = 0x0240;
 SPI1CON1bits = 0x0242;
_SPI1CON1bits = 0x0242;
 SPI1CON2bits = 0x0244;
_SPI1CON2bits = 0x0244;
 TRISAbits = 0x02C0;
_TRISAbits = 0x02C0;
 PORTAbits = 0x02C2;
_PORTAbits = 0x02C2;
 LATAbits = 0x02C4;
_LATAbits = 0x02C4;
 TRISBbits = 0x02C6;
_TRISBbits = 0x02C6;
 PORTBbits = 0x02C8;
_PORTBbits = 0x02C8;
 LATBbits = 0x02CA;
_LATBbits = 0x02CA;
 TRISDbits = 0x02D2;
_TRISDbits = 0x02D2;
 PORTDbits = 0x02D4;
_PORTDbits = 0x02D4;
 LATDbits = 0x02D6;
_LATDbits = 0x02D6;
 TRISEbits = 0x02D8;
_TRISEbits = 0x02D8;
 PORTEbits = 0x02DA;
_PORTEbits = 0x02DA;
 LATEbits = 0x02DC;
_LATEbits = 0x02DC;
 TRISFbits = 0x02DE;
_TRISFbits = 0x02DE;
 PORTFbits = 0x02E0;
_PORTFbits = 0x02E0;
 LATFbits = 0x02E2;
_LATFbits = 0x02E2;
 TRISGbits = 0x02E4;
_TRISGbits = 0x02E4;
 PORTGbits = 0x02E6;
_PORTGbits = 0x02E6;
 LATGbits = 0x02E8;
_LATGbits = 0x02E8;
 ADCONbits = 0x0300;
_ADCONbits = 0x0300;
 ADPCFGbits = 0x0302;
_ADPCFGbits = 0x0302;
 ADSTATbits = 0x0306;
_ADSTATbits = 0x0306;
 ADCPC0bits = 0x030A;
_ADCPC0bits = 0x030A;
 ADCPC1bits = 0x030C;
_ADCPC1bits = 0x030C;
 ADCPC2bits = 0x030E;
_ADCPC2bits = 0x030E;
 PTCONbits = 0x0400;
_PTCONbits = 0x0400;

 PWMCON1bits = 0x0408;
_PWMCON1bits = 0x0408;
 IOCON1bits = 0x040A;
_IOCON1bits = 0x040A;
 FCLCON1bits = 0x040C;
_FCLCON1bits = 0x040C;
 TRIG1bits = 0x0416;
_TRIG1bits = 0x0416;
 TRGCON1bits = 0x0418;
_TRGCON1bits = 0x0418;
 LEBCON1bits = 0x041A;
_LEBCON1bits = 0x041A;

 PWMCON2bits = 0x041C;
_PWMCON2bits = 0x041C;
 IOCON2bits = 0x041E;
_IOCON2bits = 0x041E;
 FCLCON2bits = 0x0420;
_FCLCON2bits = 0x0420;
 TRGCON2bits = 0x042C;
_TRGCON2bits = 0x042C;
 LEBCON2bits = 0x042E;
_LEBCON2bits = 0x042E;

 PWMCON3bits = 0x0430;
_PWMCON3bits = 0x0430;
 IOCON3bits = 0x0432;
_IOCON3bits = 0x0432;
 FCLCON3bits = 0x0434;
_FCLCON3bits = 0x0434;
 TRGCON3bits = 0x0440;
_TRGCON3bits = 0x0440;
 LEBCON3bits = 0x0442;
_LEBCON3bits = 0x0442;

 PWMCON4bits = 0x0444;
_PWMCON4bits = 0x0444;
 IOCON4bits = 0x0446;
_IOCON4bits = 0x0446;
 FCLCON4bits = 0x0448;
_FCLCON4bits = 0x0448;
 TRGCON4bits = 0x0454;
_TRGCON4bits = 0x0454;
 LEBCON4bits = 0x0456;
_LEBCON4bits = 0x0456;

 CMPCON1bits = 0x04C0;
_CMPCON1bits = 0x04C0;
 CMPDAC1bits = 0x04C2;
_CMPDAC1bits = 0x04C2;
 CMPCON2bits = 0x04C4;
_CMPCON2bits = 0x04C4;
 CMPDAC2bits = 0x04C6;
_CMPDAC2bits = 0x04C6;
 CMPCON3bits = 0x04C8;
_CMPCON3bits = 0x04C8;
 CMPDAC3bits = 0x04CA;
_CMPDAC3bits = 0x04CA;
 CMPCON4bits = 0x04CC;
_CMPCON4bits = 0x04CC;
 CMPDAC4bits = 0x04CE;
_CMPDAC4bits = 0x04CE;

 RCONbits = 0x0740;
_RCONbits = 0x0740;
 OSCCONbits = 0x0742;
_OSCCONbits = 0x0742;
 OSCTUNbits = 0x0748;
_OSCTUNbits = 0x0748;
 OSCTUN2bits = 0x074A;
_OSCTUN2bits = 0x074A;
 NVMCONbits = 0x0760;
_NVMCONbits = 0x0760;
 PMD1bits = 0x0770;
_PMD1bits = 0x0770;
 PMD2bits = 0x0772;
_PMD2bits = 0x0772;
 PMD3bits = 0x0774;
_PMD3bits = 0x0774;
/*
**end of SFR definitions required for C header
*/

/* SFR base address definitions for various peripherals */

 OC1 = 0x0180;
_OC1 = 0x0180;
 OC2 = 0x0186;
_OC2 = 0x0186;

 UART1 = 0x0220;
_UART1 = 0x0220;

 SPI1 = 0x0240;
_SPI1 = 0x0240;

/*=========================================================================
**end of SFR definitions required in Data Space
*========================================================================*/
