<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE codeDefinitions SYSTEM "../codeDefinitions.dtd" >
<codeDefinitions>
	<codeBlock>
		<code name="fuses" caption="fuses (DCR) configuration">
			<line comment="B1=GCP B0=GWRP"></line>
			<line register="FGS" action="WCFG" mask="0xFFFF" comment=""></line>
			<line comment="B2:0=FNOSC2:0"></line>
			<line register="FOSCSEL" action="WCFG" mask="0xFFFF" comment=""></line>
			<line comment="B7:6=FCKSM1:0 B2=OSCIOFNC B1:0=POSCMD1:0"></line>
			<line register="FOSC" action="WCFG" mask="0xFFFF" comment=""></line>
			<line comment="B7=FWDTEN B6=WINDIS B4=WDTPRE B3:0=WDTPOST3:0"></line>
			<line register="FWDT" action="WCFG" mask="0xFFFF" comment=""></line>
			<line comment="B3=PWRTEN B2:0=FPWRT2:0"></line>
			<line register="FPOR" action="WCFG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="Interrupts" caption="Disable Interrupts during configuration">
			<line comment="clear int flags:"></line>
			<line comment="B14=DMA1 B13=AD1 B12=U1TX B11=U1RX B10=SPI1 B9=SPI1E B8=T3"></line>
			<line comment="B7=T2 B6=OC2 B5=IC2 B4=DMA0 B3=T1 B2=OC1 B1=IC1 B0=INT0"></line>
			<line register="IFS0" action="W" value="0x0000" mask="0xFFFF" comment=""></line>
			<line comment="B15=U2TX B14=U2RX B13=INT2 B12=T5 B11=T4 B10=OC4 B9=OC3 B8=DMA2"></line>
			<line comment="B7=IC8 B6=IC7 B5=AD2 B4=INT1 B3=CN B1=MI2C1 B0=SI2C1"></line>
			<line register="IFS1" action="W" value="0x0000" mask="0xFFFF" comment=""></line>
			<line comment="B15=T6 B14=DMA4 B12:9=OC8:5 B8=IC6"></line>
			<line comment="B7=IC5 B6=IC4 B5=IC3 B4=DMA3 B3=C1 B2=C1RX B1=SPI2 B0=SPI2E "></line>
			<line register="IFS2" action="W" value="0x0000" mask="0xFFFF" comment=""></line>
			<line comment=" B13=DMA5 B8=C2"></line>
			<line comment="B7=C2RX B6=INT4 B5=INT3 B4=T9 B3=T8 B2=MI2C2 B1=SI2C1 B0=T7 "></line>
			<line register="IFS3" action="W" value="0x0000" mask="0xFFFF" comment=""></line>
			<line comment="B7=C2TX B6=C1TX B5=DMA7 B4=DMA6 B2=U2E B1=U1E B0=FLTB "></line>
			<line register="IFS4" action="W" value="0x0000" mask="0xFFFF" comment=""></line>
			<line register="IEC0" action="W" value="0x0000" mask="0xFFFF" comment=""></line>
			<line register="IEC1" action="W" value="0x0000" mask="0xFFFF" comment=""></line>
			<line register="IEC2" action="W" value="0x0000" mask="0xFFFF" comment=""></line>
			<line register="IEC3" action="W" value="0x0000" mask="0xFFFF" comment=""></line>
			<line register="IEC4" action="W" value="0x0000" mask="0xFFFF" comment=""></line>
			
		</code>
		<code name="Reset" caption="Reset configuration">
			<line comment="B15=TRAPR B14=IOPUWR B13=BGST B8=VREGS"></line>
			<line comment="B7=EXTR B6=SWR B5=SWDTEN B4=WDTO B3=SLEEP B2=IDLE B1=BOR B0=POR"></line>
			<line register="RCON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="NVM" caption="NVM configuration - not implemented">
    </code>
		<code name="Oscillator" caption="Oscillator configuration">
			<line comment="method to override OSCCON write protect"></line>
			<line comment="B13:12=COSC1:0 B9:8=NOSC1:0"></line>
			<line register="OSCCON" action="LREG.b_H" value="WREG" mask="0x00FF" comment=""></line>
			<line register="W1" action="W.b_H" value="0x78" mask="0x00FF" comment=""></line>
			<line register="W2" action="W.b_H" value="0x9A" mask="0x00FF" comment=""></line>
			<line code="MOV.W #OSCCON, W3" comment=""></line>
			<line code="MOV.B W1, [W3+1]" comment=""></line>
			<line code="MOV.B W2, [W3+1]" comment=""></line>
			<line code="MOV.B W0, [W3+1]" comment=""></line>
			<line comment="B7=CLKLOCK B5=LOCK B3=CF B1=LPOSCEN B0=OSWEN"></line>
			<line register="OSCCON" action="LREG.b_L" value="WREG" mask="0x00FF" comment=""></line>
			<line register="W1" action="W.b_L" value="0x46" mask="0x00FF" comment=""></line>
			<line register="W2" action="W.b_L" value="0x57" mask="0x00FF" comment=""></line>
			<line code="MOV.B W1, [W3+0]" comment=""></line>
			<line code="MOV.B W2, [W3+0]" comment=""></line>
			<line code="MOV.B W0, [W3+0]" comment=""></line>
			
			<line comment="B15=ROI B14:12=DOZE2:0 B11=DOZEN B10:8=FRCDIV2:0"></line>
			<line comment="B7:6=PLLPOST1:0 B4:0=PLLPRE4:0"></line>
            <line register="CLKDIV" action="WREG" mask="0xFFDF" comment=""></line>
            <line comment="B8:0=PLLDIV8:0"></line>
            <line register="PLLFBD" action="WREG" mask="0x003F" comment=""></line>
			<line comment="B5:0=TUN5:0"></line>
            <line register="OSCTUN" action="WREG" mask="0x00DF" comment=""></line>
            
		</code>
		<code name="A2D" caption="A2D configuration">
			<line register="ADPCFG" action="W" value="0xFFFF" mask="0xFFFF" comment="force all A2D ports to digital IO at first"></line>
		</code>
		<code name="IOPortA" caption="IO Ports configuration">
			<line comment="B15:0=A15:0"></line>
			<line register="PORTA" action="WREG" mask="0xFFFF" comment="enable"></line>
			<line register="TRISA" action="WREG" mask="0xFFFF" comment="direction in=1"></line>
			<line register="ODCA" action="WREG" mask="0xFFFF" comment="direction in=1"></line>
		</code>
		<code name="IOPortB" caption="IO Ports configuration">
			<line comment="B15:0=B15:0"></line>
			<line register="PORTB" action="WREG" mask="0xFFFF" comment="enable"></line>
			<line register="TRISB" action="WREG" mask="0xFFFF" comment="direction in=1"></line>
		</code>
		<code name="IOPortC" caption="IO Ports configuration">
			<line comment="B15:0=C15:0"></line>
			<line register="PORTC" action="WREG" mask="0xFFFF" comment="enable"></line>
			<line register="TRISC" action="WREG" mask="0xFFFF" comment="direction in=1"></line>
		</code>
		<code name="IOPortD" caption="IO Ports configuration">
			<line comment="B15:0=D15:0"></line>
			<line register="PORTD" action="WREG" mask="0xFFFF" comment="enable"></line>
			<line register="TRISD" action="WREG" mask="0xFFFF" comment="direction in=1"></line>
			<line register="ODCD" action="WREG" mask="0xFFFF" comment="direction in=1"></line>
		</code>
		<code name="IOPortE" caption="IO Ports configuration">
			<line comment="B15:0=D15:0"></line>
			<line register="PORTE" action="WREG" mask="0xFFFF" comment="enable"></line>
			<line register="TRISE" action="WREG" mask="0xFFFF" comment="direction in=1"></line>
		</code>
		<code name="IOPortF" caption="IO Ports configuration">
			<line comment="B15:0=F15:0"></line>
			<line register="PORTF" action="WREG" mask="0xFFFF" comment="enable"></line>
			<line register="TRISF" action="WREG" mask="0xFFFF" comment="direction in=1"></line>
			<line register="ODCF" action="WREG" mask="0xFFFF" comment="direction in=1"></line>
		</code>
		<code name="IOPortG" caption="IO Ports configuration">
			<line comment="B15:0=G15:0"></line>
			<line register="PORTG" action="WREG" mask="0xFFFF" comment="enable"></line>
			<line register="TRISG" action="WREG" mask="0xFFFF" comment="direction in=1"></line>
			<line register="ODCG" action="WREG" mask="0xFFFF" comment="direction in=1"></line>
		</code>
		<code name="CN1" caption="Input Change Notification configuration">
			<line comment="B15:0=CN15:0"></line>
			<line register="CNEN1" action="WREG" mask="0xFFFF" comment="enable change notification"></line>
			<line register="CNPU1" action="WREG" mask="0xFFFF" comment="enable pullup change notification"></line>
			<line comment="B15:0=CN23:16 B7:0=CN7:0"></line>
			<line register="CNEN2" action="WREG" mask="0x003F" comment="enable change notification"></line>
			<line register="CNPU2" action="WREG" mask="0x003F" comment="enable pullup change notification"></line>
		</code>
    <code name="CPU" caption="CPU register configuration">
			<line register="SR" action="WMAN" value="0x0000" mask="0xFFFF" comment=""></line>
			<line register="SR" action="WREGMAN" mask="0xFFFF" comment=""></line>
			<line register="W0" action="WMAN" value="0x0000" mask="0xFFFF" comment=""></line>
			<line register="W1" action="WMAN" value="0x0000" mask="0xFFFF" comment=""></line>
			<line register="W2" action="WMAN" value="0x0000" mask="0xFFFF" comment=""></line>
		</code>
		<code name="Timer1" caption="Timers configuration">
			<line register="T1CON" action="W" value="0x0000" mask="0xFFFF" comment="stop timer"></line>
		</code>
		<code name="Timer2" caption="Timers configuration">
			<line register="T2CON" action="W" value="0x0000" mask="0xFFFF" comment="stop timer"></line>
		</code>
		<code name="Timer3" caption="Timers configuration">
			<line register="T3CON" action="W" value="0x0000" mask="0xFFFF" comment="stop timer"></line>
		</code>
		<code name="Timer4" caption="Timers configuration">
			<line register="T4CON" action="W" value="0x0000" mask="0xFFFF" comment="stop timer"></line>
		</code>
		<code name="Timer5" caption="Timers configuration">
			<line register="T5CON" action="W" value="0x0000" mask="0xFFFF" comment="stop timer"></line>
		</code>
		<code name="Timer6" caption="Timers configuration">
			<line register="T6CON" action="W" value="0x0000" mask="0xFFFF" comment="stop timer"></line>
		</code>
		<code name="Timer7" caption="Timers configuration">
			<line register="T7CON" action="W" value="0x0000" mask="0xFFFF" comment="stop timer"></line>
		</code>
		<code name="Timer8" caption="Timers configuration">
			<line register="T8CON" action="W" value="0x0000" mask="0xFFFF" comment="stop timer"></line>
		</code>
		<code name="Timer9" caption="Timers configuration">
			<line register="T9CON" action="W" value="0x0000" mask="0xFFFF" comment="stop timer"></line>
		</code>
		<code name="Timer1" caption="Timers configuration">
			<line register="TMR1" action="WREG" mask="0xFFFF" comment="timer register"></line>
			<line register="PR1" action="WREG" mask="0xFFFF" comment="period register"></line>
		</code>
		<code name="Timer3" caption="Timers configuration">
			<line register="TMR3" action="WREG" mask="0xFFFF" comment="timer register"></line>
			<line register="TMR3HLD" action="WREG" mask="0xFFFF" comment="timer holding register for 32bit"></line>
			<line register="PR3" action="WREG" mask="0xFFFF" comment="period register"></line>
		</code>
		<code name="Timer2" caption="Timers configuration">
			<line register="TMR2" action="WREG" mask="0xFFFF" comment="timer register"></line>
			<line register="PR2" action="WREG" mask="0xFFFF" comment="period register"></line>
		</code>
		<code name="Timer5" caption="Timers configuration">
			<line register="TMR4" action="WREG" mask="0xFFFF" comment="timer register"></line>
			<line register="PR4" action="WREG" mask="0xFFFF" comment="period register"></line>
		</code>
		<code name="Timer4" caption="Timers configuration">
			<line register="TMR5" action="WREG" mask="0xFFFF" comment="timer register"></line>
			<line register="TMR5HLD" action="WREG" mask="0xFFFF" comment="timer holding register for 32bit"></line>
			<line register="PR5" action="WREG" mask="0xFFFF" comment="period register"></line>
		</code>
		<code name="Timer6" caption="Timers configuration">
			<line register="TMR6" action="WREG" mask="0xFFFF" comment="timer register"></line>
			<line register="PR6" action="WREG" mask="0xFFFF" comment="period register"></line>
		</code>
		<code name="Timer7" caption="Timers configuration">
			<line register="TMR7" action="WREG" mask="0xFFFF" comment="timer register"></line>
			<line register="TMR7HLD" action="WREG" mask="0xFFFF" comment="timer holding register for 32bit"></line>
			<line register="PR7" action="WREG" mask="0xFFFF" comment="period register"></line>
		</code>
		<code name="Timer8" caption="Timers configuration">
			<line register="TMR8" action="WREG" mask="0xFFFF" comment="timer register"></line>
			<line register="PR8" action="WREG" mask="0xFFFF" comment="period register"></line>
		</code>
		<code name="Timer9" caption="Timers configuration">
			<line register="TMR9" action="WREG" mask="0xFFFF" comment="timer register"></line>
			<line register="TMR9HLD" action="WREG" mask="0xFFFF" comment="timer holding register for 32bit"></line>
			<line register="PR9" action="WREG" mask="0xFFFF" comment="period register"></line>
		</code>
		<code name="IC1" caption="Input Capture configuration">
			<line comment="B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0"></line>
			<line register="IC1CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="IC2" caption="Input Capture configuration">
			<line comment="B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0"></line>
			<line register="IC2CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="IC3" caption="Input Capture configuration">
			<line comment="B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0"></line>
			<line register="IC3CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="IC4" caption="Input Capture configuration">
			<line comment="B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0"></line>
			<line register="IC4CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="IC5" caption="Input Capture configuration">
			<line comment="B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0"></line>
			<line register="IC5CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="IC6" caption="Input Capture configuration">
			<line comment="B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0"></line>
			<line register="IC6CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="IC7" caption="Input Capture configuration">
			<line comment="B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0"></line>
			<line register="IC7CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="IC8" caption="Input Capture configuration">
		    <line comment="B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0"></line>
			<line register="IC8CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="OC1" caption="Turn off OC1 thru OC8">
			<line comment="associated timers need to be turned off first"></line>
			<line register="OC1CON" action="W" value="0x0000" mask="0xFFFF" comment=""></line>
		</code>
		<code name="OC2" caption="Turn off OC1 thru OC8">
			<line comment="associated timers need to be turned off first"></line>
			<line register="OC2CON" action="W" value="0x0000" mask="0xFFFF" comment=""></line>
		</code>
		<code name="OC3" caption="Turn off OC1 thru OC8">
			<line comment="associated timers need to be turned off first"></line>
			<line register="OC3CON" action="W" value="0x0000" mask="0xFFFF" comment=""></line>
		</code>
		<code name="OC4" caption="Turn off OC1 thru OC8">
			<line comment="associated timers need to be turned off first"></line>
			<line register="OC4CON" action="W" value="0x0000" mask="0xFFFF" comment=""></line>
		</code>
		<code name="OC5" caption="Turn off OC1 thru OC8">
			<line comment="associated timers need to be turned off first"></line>
			<line register="OC5CON" action="W" value="0x0000" mask="0xFFFF" comment=""></line>
		</code>
		<code name="OC6" caption="Turn off OC1 thru OC8">
			<line comment="associated timers need to be turned off first"></line>
			<line register="OC6CON" action="W" value="0x0000" mask="0xFFFF" comment=""></line>
		</code>
		<code name="OC7" caption="Turn off OC1 thru OC8">
			<line comment="associated timers need to be turned off first"></line>
			<line register="OC7CON" action="W" value="0x0000" mask="0xFFFF" comment=""></line>
		</code>
		<code name="OC8" caption="Turn off OC1 thru OC8">
			<line comment="associated timers need to be turned off first"></line>
			<line register="OC8CON" action="W" value="0x0000" mask="0xFFFF" comment=""></line>
		</code>
		<code name="OC1" caption="Output Compare configuration">
			<line comment="OCnRS:  output compare n secondary register"></line>
			<line comment="OCnR:   output compare 1 main register"></line>
			<line comment="OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0"></line>
			<line register="OC1RS" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="OC1R" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="OC1CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="OC2" caption="Output Compare configuration">
			<line comment="OCnRS:  output compare n secondary register"></line>
			<line comment="OCnR:   output compare 1 main register"></line>
			<line comment="OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0"></line>
			<line register="OC2RS" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="OC2R" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="OC2CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="OC3" caption="Output Compare configuration">
			<line comment="OCnRS:  output compare n secondary register"></line>
			<line comment="OCnR:   output compare 1 main register"></line>
			<line comment="OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0"></line>
			<line register="OC3RS" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="OC3R" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="OC3CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="OC4" caption="Output Compare configuration">
			<line comment="OCnRS:  output compare n secondary register"></line>
			<line comment="OCnR:   output compare 1 main register"></line>
			<line comment="OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0"></line>
			<line register="OC4RS" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="OC4R" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="OC4CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="OC5" caption="Output Compare configuration">
			<line comment="OCnRS:  output compare n secondary register"></line>
			<line comment="OCnR:   output compare 1 main register"></line>
			<line comment="OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0"></line>
			<line register="OC5RS" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="OC5R" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="OC5CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="OC6" caption="Output Compare configuration">
			<line comment="OCnRS:  output compare n secondary register"></line>
			<line comment="OCnR:   output compare 1 main register"></line>
			<line comment="OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0"></line>
			<line register="OC6RS" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="OC6R" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="OC6CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="OC7" caption="Output Compare configuration">
			<line comment="OCnRS:  output compare n secondary register"></line>
			<line comment="OCnR:   output compare 1 main register"></line>
			<line comment="OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0"></line>
			<line register="OC7RS" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="OC7R" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="OC7CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="OC8" caption="Output Compare configuration">
			<line comment="OCnRS:  output compare n secondary register"></line>
			<line comment="OCnR:   output compare 1 main register"></line>
			<line comment="OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0"></line>
			<line register="OC8RS" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="OC8R" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="OC8CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="SPI1" caption="SPI configuration">
			<line comment="SPInBUF:    SPI n buffer"></line>
			<line comment="SPInSTAT:   B15=SPIEN B13=SPISIDL B6=SPIROV B1=SPITBF B0=SPIRBF"></line>
			<line comment="SPInCON1(H): B12=DISSCK B11=DISSDO B10=MODE16 B9=SMP B8=CKE"></line>
			<line comment="SPInCON1(L): B7=SSEN B6=CKP B5=MSTEN B4:2=SPRE2:0 B1:0=PPRE1:0"></line>
			<line comment="SPInCON2(H): B15=FRMEN B14=SPIFSD B13=FRMPOL"></line>
			<line comment="SPInCON2(L): B1=FRMDLY"></line>
			<line register="SPI1BUF" action="R" mask="0xFFFF" comment=""></line>
			<line register="SPI1CON1" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="SPI1CON2" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="SPI1STAT" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="SPI2" caption="SPI configuration">
			<line comment="SPInBUF:    SPI n buffer"></line>
			<line comment="SPInSTAT:   B15=SPIEN B13=SPISIDL B6=SPIROV B1=SPITBF B0=SPIRBF"></line>
			<line comment="SPInCON1(H): B12=DISSCK B11=DISSDO B10=MODE16 B9=SMP B8=CKE"></line>
			<line comment="SPInCON1(L): B7=SSEN B6=CKP B5=MSTEN B4:2=SPRE2:0 B1:0=PPRE1:0"></line>
			<line comment="SPInCON2(H): B15=FRMEN B14=SPIFSD B13=FRMPOL"></line>
			<line comment="SPInCON2(L): B1=FRMDLY"></line>
			<line register="SPI2BUF" action="R" mask="0xFFFF" comment=""></line>			
			<line register="SPI2CON1" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="SPI2CON2" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="SPI2STAT" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="I2C1" caption="I2C configuration">
			<line comment="B7:0: receive register bits7:0"></line>
			<line register="I2C1RCV" action="R" mask="0x00FF" comment=""></line>
			<line comment="B9:0: address register bits9:0"></line>
			<line register="I2C1ADD" action="WREG" mask="0x03FF" comment=""></line>
			<line comment="B8:0: baud rate generator bits 8:0"></line>
			<line register="I2C1BRG" action="WREG" mask="0x01FF" comment=""></line>
			<line comment="B15=ACKSTAT B14=TRSTAT B10=BCL B9=GCSTAT B8=ADD10"></line>
			<line comment="B7=IWCOL B6=I2COV B5=D_A B4=P B3=S B2=R_W B1=RBF B0=TBF"></line>
			<line register="I2C1STAT" action="WREG" mask="0xC7FF" comment=""></line>
			<line comment="B15=I2CEN B13=I2CSIDL B12=SCLREL B11=IPMIEN B10=A10M B9=DISSLW B8=SMEN"></line>
			<line comment="B7=GCEN B6=STREN B5=ACKDT B4=ACKEN B3=RCEN B2=PEN B1=RSEN B0=SEN"></line>
			<line register="I2C1CON" action="WREG" mask="0xBFFF" comment=""></line>
		</code>
		<code name="I2C2" caption="I2C configuration">
			<line comment="B7:0: receive register bits7:0"></line>
			<line register="I2C2RCV" action="R" mask="0x00FF" comment=""></line>
			<line comment="B9:0: address register bits9:0"></line>
			<line register="I2C2ADD" action="WREG" mask="0x03FF" comment=""></line>
			<line comment="B8:0: baud rate generator bits 8:0"></line>
			<line register="I2C2BRG" action="WREG" mask="0x01FF" comment=""></line>
			<line comment="B15=ACKSTAT B14=TRSTAT B10=BCL B9=GCSTAT B8=ADD10"></line>
			<line comment="B7=IWCOL B6=I2COV B5=D_A B4=P B3=S B2=R_W B1=RBF B0=TBF"></line>
			<line register="I2C2STAT" action="WREG" mask="0xC7FF" comment=""></line>
			<line comment="B15=I2CEN B13=I2CSIDL B12=SCLREL B11=IPMIEN B10=A10M B9=DISSLW B8=SMEN"></line>
			<line comment="B7=GCEN B6=STREN B5=ACKDT B4=ACKEN B3=RCEN B2=PEN B1=RSEN B0=SEN"></line>
			<line register="I2C2CON" action="WREG" mask="0xBFFF" comment=""></line>
		</code>
		<code name="UART1" caption="UART 1 configuration">
			<line register="U1BRG" action="WREG" mask="0xFFFF" comment="UART1 baud rate generator"></line>
			<line register="U1MODE" action="W" value="0x8000" mask="0xFFFF" comment="enabling UART flushes buffers"></line>
			<line comment="B15=UTXISEL1 B14=UTXINV B13=UTXISEL0 B11=UTXBRK B10=UTXEN B9=UTXBF B8=TRMT"></line>
			<line comment="B7:6=URXISEL1:0 B5=ADDEN B4=RIDLE B3=PERR B2=FERR B1=OERR B0=URXDA"></line>
			<line register="U1STA" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15=UARTEN B13=USIDL B12=IREN B11=RTSMD B9:8=UEN1:0"></line>
			<line comment="B7=WAKE B6=LPBACK B5=ABAUD B4=RXINV B3=BRGH B2:1=PDSEL1:0 B0=STSEL"></line>
			<line register="U1MODE" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="UART2" caption="UART 2 configuration">
			<line register="U2BRG" action="WREG" mask="0xFFFF" comment="UART2 baud rate generator"></line>
			<line register="U2MODE" action="W" value="0x8000" mask="0xFFFF" comment="enabling UART flushes buffers"></line>
			<line comment="B15=UTXISEL1 B14=UTXINV B13=UTXISEL0 B11=UTXBRK B10=UTXEN B9=UTXBF B8=TRMT"></line>
			<line comment="B7:6=URXISEL1:0 B5=ADDEN B4=RIDLE B3=PERR B2=FERR B1=OERR B0=URXDA"></line>
			<line register="U2STA" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15=UARTEN B13=USIDL B12=IREN B11=RTSMD B9:8=UEN1:0"></line>
			<line comment="B7=WAKE B6=LPBACK B5=ABAUD B4=RXINV B3=BRGH B2:1=PDSEL1:0 B0=STSEL"></line>
			<line register="U2MODE" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="CAN1" caption="CAN bus configuration">
			<line comment="Always abort pending TX before init."></line>
			<line code="MOV C1CTRL1, W0" comment="get current settings"></line>
			<line code="BSET W0, #12" comment="set 'abort pending TX' bit"></line>
			<line code="MOV W0, C1CTRL1" comment="write to register"></line>
			<line code="MOV #0x1000, W1" comment="mask for status bit"></line>
			<line label="CAN1_TX_WAIT" comment=" wait for PIC to signal pending"></line>
			<line code="MOV C1CTRL1, W0" comment="has been aborted"></line>
			<line code="AND W1, W0, W0" comment=""></line>
			<line code="BRA NZ, CAN1_TX_WAIT" comment="status bit cleared when done"></line>
			<line comment="Request CAN module go into config mode so"></line>
			<line comment="we can update configuration registers."></line>
			<line code="MOV C1CTRL1, W0" comment="get current control settings"></line>
			<line code="BCLR W0, #8" comment="clear request config bits"></line>
			<line code="BCLR W0, #9" comment="clear request config bits"></line>
			<line code="BCLR W0, #10" comment="clear request config bits"></line>
			<line code="BSET W0, #10" comment="set config mode bits"></line>
			<line code="MOV W0, C1CTRL1" comment="send request"></line>
			<line comment="Loop until current mode is 'config'."></line>
			<line code="MOV #0x0080, W1" comment="config mode setting"></line>
			<line code="MOV #0x00E0, W2" comment="mask for current mode bits"></line>
			<line label="CAN1_CONFIG_WAIT" comment=""></line>
			<line code="MOV C1CTRL1, W0" comment="get status"></line>
			<line code="AND W2, W0, W0" comment="mask off current mode bits"></line>
			<line code="SUB W1, W0, W0" comment="compare to config mode value"></line>
			<line code="BRA NZ, CAN1_CONFIG_WAIT" comment="loop back if no match"></line>
			<line comment="RXFnSID: B15:5=RXFnSID10:0 B3=EXIDEN RXFnEID: B1:0=RXFnEID17:16"></line>
			<line comment="RXFnEID: B15:0=EID15:0"></line>
			<line register="C1RXF0SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF0EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF1SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF1EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF2SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF2EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF3SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF3EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF4SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF4EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF5SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF5EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF6SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF6EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF7SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF7EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF8SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF8EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF9SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF9EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF10SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF10EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF11SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF11EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF12SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF12EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF13SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF13EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF14SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF14EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF15SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXF15EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="RXMnSID: B15:5=RXFnSID10:0 B1:0=EID17:16"></line>
			<line comment="RXMnEID: B15:0=EID15:0"></line>
			<line register="C1RXM0SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXM0EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXM1SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXM1EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXM2SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1RXM2EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="TRBnSTAT: B12:8=FILHIT4:0"></line>
      <line comment="TRBnSID: B12:2=TRBnSID10:0 B1=SRR B0=IDE"></line>
			<line comment="TRBnEID: B11:0=EID17:6"></line>
			<line comment="TRBnDLC: B15:10=EID5:0 B9=RTR B8=RB1 B4=RB0 B3:0=DLC3:0"></line>
			<line register="C1TRB31SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB31EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB31DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
		  <line register="C1TRB31STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB30SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB30EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB30DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			 <line register="C1TRB30STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB29SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB29EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB29DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
      <line register="C1TRB29STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB28SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB28EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB28DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB28STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB27SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB27EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB27DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB27STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB26SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB26EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB26DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB26STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB25SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB25EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB25DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB25STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB24SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB24EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB24DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB24STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB23SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB23EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB23DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB23STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB22SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB22EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB22DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB22STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB21SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB21EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB21DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB21STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB20SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB20EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB20DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB20STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB19SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB19EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB19DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB19STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB18SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB18EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB18DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB18STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB17SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB17EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB17DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
		  <line register="C1TRB17STAT" action="DECLARE" mask="0xFFFF" comment=""></line>	
			<line register="C1TRB16SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB16EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB16DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
		  <line register="C1TRB16STAT" action="DECLARE" mask="0xFFFF" comment=""></line>	
			<line register="C1TRB15SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB15EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB15DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB15STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB14SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB14EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB14DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB14STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB13SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB13EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB13DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB13STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB12SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB12EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB12DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB12STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB11SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB11EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB11DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB11STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB10SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB10EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB10DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB10STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB9SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB9EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB9DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB9STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB8SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB8EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB8DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB8STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB7SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB7EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB7DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB7STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB6SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB6EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB6DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB6STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB5SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB5EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB5DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
		  <line register="C1TRB5STAT" action="DECLARE" mask="0xFFFF" comment=""></line>	
			<line register="C1TRB4SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB4EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB4DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB4STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB3SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB3EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB3DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB3STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB2SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB2EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB2DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB2STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB1SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB1EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB1DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB1STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB0SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB0EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB0DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C1TRB0STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			
			<line comment="B15:0=RXFUL15:0"></line>
			<line register="C1RXFUL1" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0=RXFUL31:16"></line>
			<line register="C1RXFUL2" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0=RXOVF15:0"></line>
			<line register="C1RXOVF1" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0=RXOVF31:16"></line>
			<line register="C1RXOVF2" action="WREG" mask="0xFFFF" comment=""></line>
			
			<line comment="B15=TXEN1 B14=TXABT1 B13=TXLARB1 B12=TXERR1 B11=TXREQ1 B10=RTREN1 B9:8=TX1PRI1:0 "></line>
			<line comment="B7=TXEN0 B6=TXABT0 B5=TXLARB0 B4=TXERR0 B3=TXREQ0 B2=RTREN0 B9:8=TX0PRI1:0 "></line>
			<line register="C1TR01CON" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15=TXEN3 B14=TXABT3 B13=TXLARB3 B12=TXERR3 B11=TXREQ3 B10=RTREN3 B9:8=TX3PRI1:0 "></line>
			<line comment="B7=TXEN2 B6=TXABT2 B5=TXLARB2 B4=TXERR2 B3=TXREQ2 B2=RTREN2 B9:8=TX2PRI1:0 "></line>
			<line register="C1TR23CON" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15=TXEN5 B14=TXABT5 B13=TXLARB5 B12=TXERR5 B11=TXREQ5 B10=RTREN5 B9:8=TX5PRI1:0 "></line>
			<line comment="B7=TXEN4 B6=TXABT4 B5=TXLARB4 B4=TXERR4 B3=TXREQ4 B2=RTREN4 B9:8=TX4PRI1:0 "></line>
			<line register="C1TR45CON" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15=TXEN7 B14=TXABT7 B13=TXLARB7 B12=TXERR7 B11=TXREQ7 B10=RTREN7 B9:8=TX7PRI1:0 "></line>
			<line comment="B7=TXEN6 B6=TXABT6 B5=TXLARB6 B4=TXERR6 B3=TXREQ6 B2=RTREN6 B9:8=TX6PRI1:0 "></line>
			<line register="C1TR67CON" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0=DATA15:0"></line>
			<line register="C1RXD" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0=DATA15:0"></line>
			<line register="C1TXD" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B7:6=SJW1:0 B5:0=BRP"></line>		
			<line register="C1CFG1" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B14=WAKFIL B10:8=SEG2PH"></line>
			<line comment="B7=SEG2PHTS B6=SAM B5:3=SEG1PH B2:0=PRSEG"></line>
			<line register="C1CFG2" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0=FLTEN15:0"></line>
			<line register="C1FEN1" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:14=F7MSK1:0 B13:12=F6MSK1:0 B11:10=F5MSK1:0 B9:8=F4MSK1:0 "></line>
			<line comment="B7:6=F3MSK1:0 B5:4=F2MSK1:0 B3:2=F1MSK1:0 B1:0=F0MSK1:0 "></line>
			<line register="C1FMSKSEL1" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:14=F15MSK1:0 B13:12=F14MSK1:0 B11:10=F13MSK1:0 B9:8=F12MSK1:0 "></line>
			<line comment="B7:6=F11MSK1:0 B5:4=F10MSK1:0 B3:2=F9MSK1:0 B1:0=F8MSK1:0 "></line>
			<line register="C1FMSKSEL2" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B13=CSIDL B12=ABAT B11=CANCKS B10:8=REQOP2:0 B7:5=OPMODE2:0 B0=WIN"></line>
			<line register="C1CTRL1" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B4:0=DNCNT"></line>
			<line register="C1CTRL2" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B12:8=FILHIT4:0 B6:0=ICODE6:0"></line>
			<line register="C1VEC" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:13=DMABS2:0 B4:0=FSA4:0"></line>
			<line register="C1FCTRL" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B13:8=FBP5:0 B5:0=FNRB5:0"></line>
			<line register="C1FIFO" action="WREG" mask="0xFFFF" comment=""></line>
			
      <line comment="Flags:B13=TXBO B12=TXBP"></line>
			<line comment="Flags: B11=RXBP B10=TXWAR B9=RXWAR B8=EWARN"></line>
			<line comment="Flags IF, Enables IE: B7=IVRI B6=WAK B5=ERR B3=FIFO B2=RBOV B1=RB B0=TB"></line>
			<line register="C1INTF" action="W" value="0x0000" mask="0xFFFF" comment="clear all flags"></line>
			<line register="C1INTE" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C1EC" action="W" value="0x0000" mask="0xFFFF" comment="clear tx and rx error registers"></line>
			<line comment="request post-config operating mode for CAN module "></line>
			<line register="C1CTRL1" action="WREG" mask="0x2700" comment="send post config settings"></line>
			<line code="MOV C1CTRL1, W1" comment="get requested mode"></line>
			<line code="MOV #0x0700, W2" comment="remove all but desired bits"></line>
			<line code="AND W1, W2, W1" comment="remove all but desired bits"></line>
			<line code="LSR W1, #0x03, W1" comment="shift bits to current mode location"></line>
			<line code="MOV #0x00E0, W2" comment="mask for current mode bits"></line>
			<line label="CAN1_OPMODE_WAIT" comment=""></line>
			<line code="MOV C1CTRL1, W0" comment="get status"></line>
			<line code="AND W2, W0, W0" comment="mask off current mode bits"></line>
			<line code="SUB W1, W0, W0" comment="compare to config mode value"></line>
			<line code="BRA NZ, CAN1_OPMODE_WAIT" comment="loop back if no match"></line>
		</code>
		<code name="CAN2" caption="CAN bus configuration">
			<line comment="Always abort pending TX before init."></line>
			<line code="MOV C2CTRL1, W0" comment="get current settings"></line>
			<line code="BSET W0, #12" comment="set 'abort pending TX' bit"></line>
			<line code="MOV W0, C2CTRL1" comment="write to register"></line>
			<line code="MOV #0x1000, W1" comment="mask for status bit"></line>
			<line label="CAN2_TX_WAIT" comment=" wait for PIC to signal pending"></line>
			<line code="MOV C2CTRL1, W0" comment="has been aborted"></line>
			<line code="AND W1, W0, W0" comment=""></line>
			<line code="BRA NZ, CAN2_TX_WAIT" comment="status bit cleared when done"></line>
			<line comment="Request CAN module go into config mode so"></line>
			<line comment="we can update configuration registers."></line>
			<line code="MOV C2CTRL1, W0" comment="get current control settings"></line>
			<line code="BCLR W0, #8" comment="clear request config bits"></line>
			<line code="BCLR W0, #9" comment="clear request config bits"></line>
			<line code="BCLR W0, #10" comment="clear request config bits"></line>
			<line code="BSET W0, #10" comment="set config mode bits"></line>
			<line code="MOV W0, C2CTRL1" comment="send request"></line>
			<line comment="Loop until current mode is 'config'."></line>
			<line code="MOV #0x0080, W1" comment="config mode setting"></line>
			<line code="MOV #0x00E0, W2" comment="mask for current mode bits"></line>
			<line label="CAN2_CONFIG_WAIT" comment=""></line>
			<line code="MOV C2CTRL1, W0" comment="get status"></line>
			<line code="AND W2, W0, W0" comment="mask off current mode bits"></line>
			<line code="SUB W1, W0, W0" comment="compare to config mode value"></line>
			<line code="BRA NZ, CAN2_CONFIG_WAIT" comment="loop back if no match"></line>
		<line comment="RXFnSID: B15:5=RXFnSID10:0 B3=EXIDEN RXFnEID: B1:0=RXFnEID17:16"></line>
			<line comment="RXFnEID: B15:0=EID15:0"></line>
			<line register="C2RXF0SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF0EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF1SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF1EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF2SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF2EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF3SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF3EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF4SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF4EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF5SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF5EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF6SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF6EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF7SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF7EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF8SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF8EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF9SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF9EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF10SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF10EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF11SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF11EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF12SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF12EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF13SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF13EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF14SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF14EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF15SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXF15EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="RXMnSID: B15:5=RXFnSID10:0 B1:0=EID17:16"></line>
			<line comment="RXMnEID: B15:0=EID15:0"></line>
			<line register="C2RXM0SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXM0EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXM1SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXM1EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXM2SID" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2RXM2EID" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="TRBnSTAT: B12:8=FILHIT4:0"></line>
      <line comment="TRBnSID: B12:2=TRBnSID10:0 B1=SRR B0=IDE"></line>
			<line comment="TRBnEID: B11:0=EID17:6"></line>
			<line comment="TRBnDLC: B15:10=EID5:0 B9=RTR B8=RB1 B4=RB0 B3:0=DLC3:0"></line>
			<line register="C2TRB31SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB31EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB31DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
		  <line register="C2TRB31STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB30SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB30EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB30DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			 <line register="C2TRB30STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB29SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB29EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB29DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
      <line register="C2TRB29STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB28SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB28EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB28DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB28STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB27SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB27EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB27DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB27STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB26SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB26EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB26DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB26STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB25SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB25EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB25DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB25STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB24SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB24EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB24DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB24STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB23SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB23EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB23DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB23STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB22SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB22EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB22DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB22STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB21SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB21EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB21DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB21STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB20SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB20EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB20DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB20STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB19SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB19EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB19DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB19STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB18SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB18EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB18DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB18STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB17SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB17EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB17DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
		  <line register="C2TRB17STAT" action="DECLARE" mask="0xFFFF" comment=""></line>	
			<line register="C2TRB16SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB16EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB16DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
		  <line register="C2TRB16STAT" action="DECLARE" mask="0xFFFF" comment=""></line>	
			<line register="C2TRB15SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB15EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB15DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB15STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB14SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB14EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB14DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB14STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB13SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB13EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB13DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB13STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB12SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB12EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB12DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB12STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB11SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB11EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB11DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB11STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB10SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB10EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB10DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB10STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB9SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB9EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB9DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB9STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB8SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB8EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB8DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB8STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB7SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB7EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB7DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB7STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB6SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB6EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB6DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB6STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB5SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB5EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB5DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
		  <line register="C2TRB5STAT" action="DECLARE" mask="0xFFFF" comment=""></line>	
			<line register="C2TRB4SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB4EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB4DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB4STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB3SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB3EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB3DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB3STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB2SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB2EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB2DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB2STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB1SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB1EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB1DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB1STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB0SID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB0EID" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB0DLC" action="DECLARE" mask="0xFFFF" comment=""></line>
			<line register="C2TRB0STAT" action="DECLARE" mask="0xFFFF" comment=""></line>
			
			<line comment="B15:0=RXFUL15:0"></line>
			<line register="C2RXFUL1" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0=RXFUL31:16"></line>
			<line register="C2RXFUL2" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0=RXOVF15:0"></line>
			<line register="C2RXOVF1" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0=RXOVF31:16"></line>
			<line register="C2RXOVF2" action="WREG" mask="0xFFFF" comment=""></line>
			
			<line comment="B15=TXEN1 B14=TXABT1 B13=TXLARB1 B12=TXERR1 B11=TXREQ1 B10=RTREN1 B9:8=TX1PRI1:0 "></line>
			<line comment="B7=TXEN0 B6=TXABT0 B5=TXLARB0 B4=TXERR0 B3=TXREQ0 B2=RTREN0 B9:8=TX0PRI1:0 "></line>
			<line register="C2TR01CON" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15=TXEN3 B14=TXABT3 B13=TXLARB3 B12=TXERR3 B11=TXREQ3 B10=RTREN3 B9:8=TX3PRI1:0 "></line>
			<line comment="B7=TXEN2 B6=TXABT2 B5=TXLARB2 B4=TXERR2 B3=TXREQ2 B2=RTREN2 B9:8=TX2PRI1:0 "></line>
			<line register="C2TR23CON" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15=TXEN5 B14=TXABT5 B13=TXLARB5 B12=TXERR5 B11=TXREQ5 B10=RTREN5 B9:8=TX5PRI1:0 "></line>
			<line comment="B7=TXEN4 B6=TXABT4 B5=TXLARB4 B4=TXERR4 B3=TXREQ4 B2=RTREN4 B9:8=TX4PRI1:0 "></line>
			<line register="C2TR45CON" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15=TXEN7 B14=TXABT7 B13=TXLARB7 B12=TXERR7 B11=TXREQ7 B10=RTREN7 B9:8=TX7PRI1:0 "></line>
			<line comment="B7=TXEN6 B6=TXABT6 B5=TXLARB6 B4=TXERR6 B3=TXREQ6 B2=RTREN6 B9:8=TX6PRI1:0 "></line>
			<line register="C2TR67CON" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0=DATA15:0"></line>
			<line register="C2RXD" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0=DATA15:0"></line>
			<line register="C2TXD" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B7:6=SJW1:0 B5:0=BRP"></line>		
			<line register="C1CFG1" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B14=WAKFIL B10:8=SEG2PH"></line>
			<line comment="B7=SEG2PHTS B6=SAM B5:3=SEG1PH B2:0=PRSEG"></line>
			<line register="C2CFG2" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0=FLTEN15:0"></line>
			<line register="C2FEN1" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:14=F7MSK1:0 B13:12=F6MSK1:0 B11:10=F5MSK1:0 B9:8=F4MSK1:0 "></line>
			<line comment="B7:6=F3MSK1:0 B5:4=F2MSK1:0 B3:2=F1MSK1:0 B1:0=F0MSK1:0 "></line>
			<line register="C2FMSKSEL1" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:14=F15MSK1:0 B13:12=F14MSK1:0 B11:10=F13MSK1:0 B9:8=F12MSK1:0 "></line>
			<line comment="B7:6=F11MSK1:0 B5:4=F10MSK1:0 B3:2=F9MSK1:0 B1:0=F8MSK1:0 "></line>
			<line register="C2FMSKSEL2" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B13=CSIDL B12=ABAT B11=CANCKS B10:8=REQOP2:0 B7:5=OPMODE2:0 B0=WIN"></line>
			<line register="C2CTRL1" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B4:0=DNCNT"></line>
			<line register="C2CTRL2" action="WREG" mask="0xFFFF" comment=""></line>
			 <line comment="B12:8=FILHIT4:0 B6:0=ICODE6:0"></line>
			<line register="C2VEC" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:13=DMABS2:0 B4:0=FSA4:0"></line>
			<line register="C2FCTRL" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B13:8=FBP5:0 B5:0=FNRB5:0"></line>
			<line register="C2FIFO" action="WREG" mask="0xFFFF" comment=""></line>
			
			<line comment="Flags:B13=TXBO B12=TXBP"></line>
			<line comment="Flags: B11=RXBP B10=TXWAR B9=RXWAR B8=EWARN"></line>
			<line comment="Flags IF, Enables IE: B7=IVRI B6=WAK B5=ERR B3=FIFO B2=RBOV B1=RB B0=TB"></line>
			<line register="C2INTF" action="W" value="0x0000" mask="0xFFFF" comment="clear all flags"></line>
			<line register="C2INTE" action="WREG" mask="0xFFFF" comment=""></line>
			<line register="C2EC" action="W" value="0x0000" mask="0xFFFF" comment="clear tx and rx error registers"></line>
			<line comment="request post-config operating mode for CAN module "></line>
			<line register="C2CTRL1" action="WREG" mask="0x2700" comment="send post config settings"></line>
			<line code="MOV C2CTRL1, W1" comment="get requested mode"></line>
			<line code="MOV #0x0700, W2" comment="remove all but desired bits"></line>
			<line code="AND W1, W2, W1" comment="remove all but desired bits"></line>
			<line code="LSR W1, #0x03, W1" comment="shift bits to current mode location"></line>
			<line code="MOV #0x00E0, W2" comment="mask for current mode bits"></line>
			<line label="CAN2_OPMODE_WAIT" comment=""></line>
			<line code="MOV C2CTRL1, W0" comment="get status"></line>
			<line code="AND W2, W0, W0" comment="mask off current mode bits"></line>
			<line code="SUB W1, W0, W0" comment="compare to config mode value"></line>
			<line code="BRA NZ, CAN2_OPMODE_WAIT" comment="loop back if no match"></line>
		</code>
		
		<code name="DMA1" caption="DMA  configuration">
			<line comment="B15:8=PWCOL7:0 B7:0=XWCOL7:0"></line>
			<line register="DMACS0" action="WREG" mask="0xF033" comment=""></line>
			<line comment="B11:8=LSTCH3:0 B7:0=PPST7:0"></line>
			<line register="DMACS1" action="WREG" mask="0x807F" comment=""></line>
			<line comment="B15:0=DSADR15:0"></line>
			<line register="DSADR" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="Initialize DMA CH0"></line>
			<line comment="B15=CHEN B14=SIZE B13=DIR B12=HALF B11=NULLW"></line>
			<line comment="B5:4=AMODE1:0 B1:0=MODE1:0"></line>
			<line register="DMA0CON" action="WREG" mask="0xF033" comment=""></line>
			<line comment="B15=FORCE B6:0=IRQSEL6:0"></line>
			<line register="DMA0REQ" action="WREG" mask="0x807F" comment=""></line>
			<line comment="B15:0: Primary DMA RAM Start Address bit15:0"></line>
			<line register="DMA0STA" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0: Secondary DMA RAM Start Address bit15:0"></line>
			<line register="DMA0STB" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0: Peripheral Address Register bits15:0"></line>
			<line register="DMA0PAD" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B9:0: Transfer Count Register bits9:0"></line>
			<line register="DMA0CNT" action="WREG" mask="0x03FF" comment=""></line>
			<line comment="Initialize DMA CH1"></line>
			<line comment="B15=CHEN B14=SIZE B13=DIR B12=HALF B11=NULLW"></line>
			<line comment="B5:4=AMODE1:0 B1:0=MODE1:0"></line>
			<line register="DMA1CON" action="WREG" mask="0xF033" comment=""></line>
			<line comment="B15=FORCE B6:0=IRQSEL6:0"></line>
			<line register="DMA1REQ" action="WREG" mask="0x807F" comment=""></line>
			<line comment="B15:0: Primary DMA RAM Start Address bit15:0"></line>
			<line register="DMA1STA" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0: Secondary DMA RAM Start Address bit15:0"></line>
			<line register="DMA1STB" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0: Peripheral Address Register bits15:0"></line>
			<line register="DMA1PAD" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B9:0: Transfer Count Register bits9:0"></line>
			<line register="DMA1CNT" action="WREG" mask="0x03FF" comment=""></line>
			<line comment="Initialize DMA CH2"></line>
			<line comment="B15=CHEN B14=SIZE B13=DIR B12=HALF B11=NULLW"></line>
			<line comment="B5:4=AMODE1:0 B1:0=MODE1:0"></line>
			<line register="DMA2CON" action="WREG" mask="0xF033" comment=""></line>
			<line comment="B15=FORCE B6:0=IRQSEL6:0"></line>
			<line register="DMA2REQ" action="WREG" mask="0x807F" comment=""></line>
			<line comment="B15:0: Primary DMA RAM Start Address bit15:0"></line>
			<line register="DMA2STA" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0: Secondary DMA RAM Start Address bit15:0"></line>
			<line register="DMA2STB" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0: Peripheral Address Register bits15:0"></line>
			<line register="DMA2PAD" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B9:0: Transfer Count Register bits9:0"></line>
			<line register="DMA2CNT" action="WREG" mask="0x03FF" comment=""></line>
			<line comment="Initialize DMA CH3"></line>
			<line comment="B15=CHEN B14=SIZE B13=DIR B12=HALF B11=NULLW"></line>
			<line comment="B5:4=AMODE1:0 B1:0=MODE1:0"></line>
			<line register="DMA3CON" action="WREG" mask="0xF033" comment=""></line>
			<line comment="B15=FORCE B6:0=IRQSEL6:0"></line>
			<line register="DMA3REQ" action="WREG" mask="0x807F" comment=""></line>
			<line comment="B15:0: Primary DMA RAM Start Address bit15:0"></line>
			<line register="DMA3STA" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0: Secondary DMA RAM Start Address bit15:0"></line>
			<line register="DMA3STB" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0: Peripheral Address Register bits15:0"></line>
			<line register="DMA3PAD" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B9:0: Transfer Count Register bits9:0"></line>
			<line register="DMA3CNT" action="WREG" mask="0x03FF" comment=""></line>
			<line comment="Initialize DMA CH4"></line>
			<line comment="B15=CHEN B14=SIZE B13=DIR B12=HALF B11=NULLW"></line>
			<line comment="B5:4=AMODE1:0 B1:0=MODE1:0"></line>
			<line register="DMA4CON" action="WREG" mask="0xF033" comment=""></line>
			<line comment="B15=FORCE B6:0=IRQSEL6:0"></line>
			<line register="DMA4REQ" action="WREG" mask="0x807F" comment=""></line>
			<line comment="B15:0: Primary DMA RAM Start Address bit15:0"></line>
			<line register="DMA4STA" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0: Secondary DMA RAM Start Address bit15:0"></line>
			<line register="DMA4STB" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0: Peripheral Address Register bits15:0"></line>
			<line register="DMA4PAD" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B9:0: Transfer Count Register bits9:0"></line>
			<line register="DMA4CNT" action="WREG" mask="0x03FF" comment=""></line>
			<line comment="Initialize DMA CH5"></line>
			<line comment="B15=CHEN B14=SIZE B13=DIR B12=HALF B11=NULLW"></line>
			<line comment="B5:4=AMODE1:0 B1:0=MODE1:0"></line>
			<line register="DMA5CON" action="WREG" mask="0xF033" comment=""></line>
			<line comment="B15=FORCE B6:0=IRQSEL6:0"></line>
			<line register="DMA5REQ" action="WREG" mask="0x807F" comment=""></line>
			<line comment="B15:0: Primary DMA RAM Start Address bit15:0"></line>
			<line register="DMA5STA" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0: Secondary DMA RAM Start Address bit15:0"></line>
			<line register="DMA5STB" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0: Peripheral Address Register bits15:0"></line>
			<line register="DMA5PAD" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B9:0: Transfer Count Register bits9:0"></line>
			<line register="DMA5CNT" action="WREG" mask="0x03FF" comment=""></line>
			<line comment="Initialize DMA CH6"></line>
			<line comment="B15=CHEN B14=SIZE B13=DIR B12=HALF B11=NULLW"></line>
			<line comment="B5:4=AMODE1:0 B1:0=MODE1:0"></line>
			<line register="DMA6CON" action="WREG" mask="0xF033" comment=""></line>
			<line comment="B15=FORCE B6:0=IRQSEL6:0"></line>
			<line register="DMA6REQ" action="WREG" mask="0x807F" comment=""></line>
			<line comment="B15:0: Primary DMA RAM Start Address bit15:0"></line>
			<line register="DMA6STA" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0: Secondary DMA RAM Start Address bit15:0"></line>
			<line register="DMA6STB" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0: Peripheral Address Register bits15:0"></line>
			<line register="DMA6PAD" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B9:0: Transfer Count Register bits9:0"></line>
			<line register="DMA6CNT" action="WREG" mask="0x03FF" comment=""></line>
			<line comment="Initialize DMA CH7"></line>
			<line comment="B15=CHEN B14=SIZE B13=DIR B12=HALF B11=NULLW"></line>
			<line comment="B5:4=AMODE1:0 B1:0=MODE1:0"></line>
			<line register="DMA7CON" action="WREG" mask="0xF033" comment=""></line>
			<line comment="B15=FORCE B6:0=IRQSEL6:0"></line>
			<line register="DMA7REQ" action="WREG" mask="0x807F" comment=""></line>
			<line comment="B15:0: Primary DMA RAM Start Address bit15:0"></line>
			<line register="DMA7STA" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0: Secondary DMA RAM Start Address bit15:0"></line>
			<line register="DMA7STB" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0: Peripheral Address Register bits15:0"></line>
			<line register="DMA7PAD" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B9:0: Transfer Count Register bits9:0"></line>
			<line register="DMA7CNT" action="WREG" mask="0x03FF" comment=""></line>
		</code>
		
		<code name="A2D1" caption="A2D 1 configuration">
			<line register="AD1CON1" action="W" value="0x0000" mask="0xFFFF" comment="Turn off A2D before setting registers"></line>
			<line comment="B15:0=CSS31:16"></line>
			<line register="AD1CSSH" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0=CSS15:0"></line>
			<line register="AD1CSSL" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B10:9=CH123NB1:0 B8=CH123SB B2:1=CH123NA1:0 B0=CH123SA"></line>
			<line register="AD1CHS123" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15=CH0NB B12:8=CH0SB4:0"></line>
			<line comment="B7=CH0NA B4:0=CH0SA4:0"></line>
			<line register="AD1CHS0" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0=PCFG31:16"></line>
			<line register="AD1PCFGH" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0=PCFG15:0"></line>
			<line register="AD1PCFGL" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B2:0=DMABL"></line>
			<line register="AD1CON4" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15=ADRC B12:8=SAMC4:0 B5:0=ADCS5:0"></line>
			<line register="AD1CON3" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:13=VCFG2:0 B10=CSCNA B9:8=CHPS"></line>
			<line comment="B7=BUFS B5:2=SMPI B1=BUFM B0=ALTS"></line>
			<line register="AD1CON2" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15=ADON B13=ADSIDL B12=ADDMBAM B10=AD12B B9:8=FORM"></line>
			<line comment="B7:5=SSRC B3=SIMSAM B2=ASAM B1=SAMP B0=DONE"></line>
			<line register="AD1CON1" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="A2D2" caption="A2D 2 configuration">
			<line register="AD2CON1" action="W" value="0x0000" mask="0xFFFF" comment="Turn off A2D before setting registers"></line>
			<line comment="B15:0=CSS15:0"></line>
			<line register="AD2CSSL" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B10:9=CH123NB1:0 B8=CH123SB B2:1=CH123NA1:0 B0=CH123SA"></line>
			<line register="AD2CHS123" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15=CH0NB B12:8=CH0SB4:0"></line>
			<line comment="B7=CH0NA B4:0=CH0SA4:0"></line>
			<line register="AD2CHS0" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:0=PCFG15:0"></line>
			<line register="AD2PCFGL" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B2:0=DMABL"></line>
			<line register="AD2CON4" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15=ADRC B12:8=SAMC4:0 B5:0=ADCS5:0"></line>
			<line register="AD2CON3" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15:13=VCFG2:0 B10=CSCNA B9:8=CHPS"></line>
			<line comment="B7=BUFS B5:2=SMPI B1=BUFM B0=ALTS"></line>
			<line register="AD2CON2" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15=ADON B13=ADSIDL B12=ADDMBAM B10=AD12B B9:8=FORM"></line>
			<line comment="B7:5=SSRC B3=SIMSAM B2=ASAM B1=SAMP B0=DONE"></line>
			<line register="AD2CON1" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="required" caption="Interrupt flags cleared and interrupt configuration">
			<line comment="interrupt priorities IP"></line>
			<line comment="B14:12=T1 B10:8=OC1 B6:4=IC1 B2:0=INTO"></line>
			<line register="IPC0" action="WREG" mask="0x7777" comment=""></line>
			<line comment="B14:12=T2 B10:8=OC2 B6:4=IC2 B2:0=DMA0"></line>
			<line register="IPC1" action="WREG" mask="0x7777" comment=""></line>
			<line comment="B14:12=U1RX B10:8=SPI1 B6:4=SPI1E B2:0=T3"></line>
			<line register="IPC2" action="WREG" mask="0x7777" comment=""></line>
			<line comment="B10:8=DMA1 B6:4=AD1 B2:0=U1TX"></line>
			<line register="IPC3" action="WREG" mask="0x0777" comment=""></line>
			<line comment="B14:12=CN B6:4=MI2C1 B2:0=SI2C1"></line>
			<line register="IPC4" action="WREG" mask="0x7077" comment=""></line>
			<line comment="B14:12=IC8 B10:8=IC7 B6:4=AD2 B2:0=INT1"></line>
			<line register="IPC5" action="WREG" mask="0x7777" comment=""></line>
			<line comment="B14:12=T4 B10:8=OC4 B6:4=OC3 B2:0=DMA2"></line>
			<line register="IPC6" action="WREG" mask="0x7777" comment=""></line>
			<line comment="B14:12=U2TX B10:8=U2RX B6:4=INT2 B2:0=T5"></line>
			<line register="IPC7" action="WREG" mask="0x7777" comment=""></line>
			<line comment="B14:12=C1 B10:8=C1RX B6:4=SPI2 B2:0=SPI2E"></line>
			<line register="IPC8" action="WREG" mask="0x7777" comment=""></line>
			<line comment="B14:12=IC5 B10:8=IC4 B6:4=IC3 B2:0=DMA3"></line>
			<line register="IPC9" action="WREG" mask="0x7777" comment=""></line>
			<line comment="B14:12=OC7 B10:8=OC6 B6:4=OC5 B2:0=IC6"></line>
			<line register="IPC10" action="WREG" mask="0x7777" comment=""></line>
			<line comment="B14:12=T6 B10:8=DMA4 B2:0=OC8"></line>
			<line register="IPC11" action="WREG" mask="0x7707" comment=""></line>
			<line comment="B14:12=T8 B10:8=MI2C2 B6:4=SI2C2 B2:0=T7"></line>
			<line register="IPC12" action="WREG" mask="0x7777" comment=""></line>
			<line comment="B14:12=C2RX B10:8=INT4 B6:4=INT3 B2:0=T9"></line>
			<line register="IPC13" action="WREG" mask="0x7777" comment=""></line>
			<line comment="B2:0=C2"></line>
			<line register="IPC14" action="WREG" mask="0x7007" comment=""></line>
			<line comment=" B6:4=DMA5 "></line>
			<line register="IPC15" action="WREG" mask="0x0070" comment=""></line>
			<line comment="B10:8=U2E B6:4=U1E "></line>
			<line register="IPC16" action="WREG" mask="0x0770" comment=""></line>
			<line comment="B14:12=C2TX B10:8=C1TX B6:4=DMA7 B2:0=DMA6"></line>
			<line register="IPC17" action="WREG" mask="0x7777" comment=""></line>
			<line comment="external interrupt enables"></line>
			<line comment="B15=NSTDIS B14=OVAERR B13=OVBERR B12=COVAERR B11=COVBERR B10=OVATE B9=OVBTE B8=COVTE"></line>
			<line comment="B7=SFTACERR B6=DIV0ERR B5=DMACERR B4=MATHERR B3=ADDRERR B2=STKERR B1=OSCFAIL"></line>
			<line register="INTCON1" action="WREG" mask="0xFFFE" comment=""></line>
			<line comment="B15=ALTIVT B14=DISI B4:0=INTnEP4:0"></line>
			<line register="INTCON2" action="WREG" mask="0xC01F" comment=""></line>
		</code>
		<code name="Timer1" caption="Start timers">
			<line comment="Timers1: B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B2=TSYNC B1=TCS"></line>
			<line register="T1CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="Timer3" caption="Start timers">
			<line comment="Timers3,5:   B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B1=TCS"></line>
			<line register="T3CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="Timer2" caption="Start timers">
			<line comment="Timers2,4:   B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B3=T32 B1=TCS"></line>
			<line register="T2CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="Timer5" caption="Start timers">
			<line comment="Timers3,5:   B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B1=TCS"></line>
			<line register="T5CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="Timer4" caption="Start timers">
			<line comment="Timers2,4:   B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B3=T32 B1=TCS"></line>
			<line register="T4CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="Timer7" caption="Start timers">
			<line comment="Timers7,9:   B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B1=TCS"></line>
			<line register="T7CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="Timer6" caption="Start timers">
			<line comment="Timers6,8:   B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B3=T32 B1=TCS"></line>
			<line register="T6CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="Timer9" caption="Start timers">
			<line comment="Timers7,9:   B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B1=TCS"></line>
			<line register="T9CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="Timer8" caption="Start timers">
			<line comment="Timers6,8:   B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B3=T32 B1=TCS"></line>
			<line register="T8CON" action="WREG" mask="0xFFFF" comment=""></line>
		</code>
		<code name="CPU" caption="CPU register configuration">
			<line register="SR" action="WMAN" value="0x0000" mask="0xFFFF" comment=""></line>
			<line register="SR" action="WREGMAN" mask="0xFFFF" comment=""></line>
			<line register="W0" action="WMAN" value="0x0000" mask="0xFFFF" comment=""></line>
			<line register="W1" action="WMAN" value="0x0000" mask="0xFFFF" comment=""></line>
			<line register="W2" action="WMAN" value="0x0000" mask="0xFFFF" comment=""></line>
		</code>
		<code name="Interrupts" caption="enable interrupts">
			<line comment="feature interrupt enables IE"></line>
			<line comment="B14=DMA1 B13=AD1 B12=U1TX B11=U1RX B10=SPI1 B9=SPI1E B8=T3"></line>
			<line comment="B7=T2 B6=OC2 B5=IC2 B4=DMA0 B3=T1 B2=OC1 B1=IC1 B0=INT0"></line>
			<line register="IEC0" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15=U2TX B14=U2RX B13=INT2 B12=T5 B11=T4 B10=OC4 B9=OC3 B8=DMA2"></line>
			<line comment="B7=IC8 B6=IC7 B5=AD2 B4=INT1 B3=CN B1=MI2C1 B0=SI2C1"></line>
			<line register="IEC1" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B15=T6 B14=DMA4 B12:9=OC8:5 B8:5=IC6:3 B4=DMA3 B3=C1 B2=C1RX B1=SPI2 B0=SPI2E "></line>
			<line register="IEC2" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B13=DMA5 B8=C2"></line>
			<line comment="B7=C2RX B6=INT4 B5=INT3 B4=T9 B3=T8 B2=MI2C2 B1=SI2C1 B0=T7 "></line>
			<line register="IEC3" action="WREG" mask="0xFFFF" comment=""></line>
			<line comment="B7=C2TX B6=C1TX B5=DMA7 B4=DMA6 B2=U2E B1=U1E "></line>
			<line register="IEC4" action="WREG" mask="0xFFFF" comment=""></line>
			<line code="return" comment="end of init"></line>
		</code>

	</codeBlock>
</codeDefinitions>
